Kang-Ill Seo

Backside Contact Resistivity Reduction for Nanosheet Technologies Beyond 2nm by Backside Nanosecond Laser Anneal Without Impacting the Frontside Cu BEOL

Ruilong Xie, Kevin Brew, Wonkeun Chung, Oleg Gluschenkov et autres

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Predictive Simulations and Experimental Study of AlN Bonding for Better Thermal Dissipation in BSPDN

Sarabjot Singh, Sangshin Jang, Prabudhya Roy Chowdhury, Ruilong Xie et autres

As the backside power delivery network (BSPDN) technology evolves, optimizing bonding materials for both thermal management and integration remains critical. In this study, we explore the optimal thickness conditions and integration strategies for aluminum nitride (AlN) bonding through simulations and experimental validation. …

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Monolithic Stacked FET with Stepped Channels for Future Logic Technologies

Chen Zhang, Jay W. Strane, Lijuan Zou, Suin Yun et autres

We present a monolithic stacked FET architecture featuring a stepped channel structure where the bottom FET channels are wider than the top. Such a design relieves high aspect ratio process challenges by reducing the total stack height and provides better performance as …

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Backside Power Distribution for Nanosheet Technologies Beyond 2nm

Ruilong Xie, Wonhyuk Hong, Chen Zhang, Joongku Lee et autres

This paper examines various approaches for integrating backside power distribution network (BSPDN) with nanosheet transistor technologies. Deep Trench Via (DTV) based BSPDN schemes, except for Shifted Frontside Via Backside Power rail (SFVBP), do not offer cell level scaling benefits, but via resistance …

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Next-generation logic design architecture for vertical-transport nanosheets

Biswanath Senapati, Jeongho Do, Daniel J. Dechene, Seunghyun Song et autres

Vertical-Transport (VTFET) Nanosheet Technology is an attractive solution to enable aggressive CMOS scaling in the sub-45nm contact-gate-pitch (CGP) regime. By decoupling the classic tradeoff of S/D contacts, gate length & contact-gate-pitch (CGP), VTFET technology overcomes middle-of-the-line (MOL) dominated performance pinch-points by providing …

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A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

Dong-il Bae, Geum-Jong Bae, Krishna Kumar Bhuwalka, Seunghun Lee et autres

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe …

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Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics

Bomsoo Kim, Dong-il Bae, PETER M. ZEITZOFF, Xin Sun et autres

The effect of positive fixed oxide charge (Qf) on the electrical characteristics of bulk FinFET devices is investigated and newly addressed as a Fin scaling detractor. The aggressively scaled Fin width leads to abnormal subthreshold slope (SS) degradation in nMOS devices even …

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Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

Kwan-Yong Lim, Hyun‐Jung Lee, Choongryul Ryu, Kang-Ill Seo et autres

High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple …

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Random Telegraph Noise in n-type and p-type silicon nanowire transistors

Seungwon Yang, Kyoung Hwan Yeo, Dong‐Won Kim, Kang-Ill Seo et autres

We studied random telegraph noise (RTN) of n-type and p-type silicon nanowire transistors (SNWT) for the first time and derived accurate vertical and lateral trap location equations in nanowire structure. Using the derived equations, accurate trap locations were extracted in the devices …

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Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?

Paul C. McIntyre, David Chi, Chi On Chui, Hyoungsub Kim et autres

We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeOxNy) and tantalum oxynitride (TaOxNy) interface layers. We find that ultrathin …

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Chemical states and electrical properties of a high-k metal oxide/silicon interface with oxygen-gettering titanium-metal-overlayer

Kang-Ill Seo, Dong-Ick Lee, P. Pianetta, Hyoungsub Kim et autres

The authors report on the chemical bonding structure of the HfO2∕Si (001) stack after the SiO2 interfacial layer (IL) is partially removed by a reactive titanium metal overlayer. Using synchrotron photoelectron spectroscopy, they found that ultrathin SiO2-like IL ∼6.5Å thick, which is …

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Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?

Paul C. McIntyre, David Chi, Chi On Chui, Hyoungsub Kim et autres

Abstract not Available.

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