PETER M. ZEITZOFF

Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures

Ali Razavieh, PETER M. ZEITZOFF, Edward Joseph Nowak

Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-Line (MOL) device parameters, is systematically investigated. It is concluded that the combined requirements of device electrostatics together with the demands on contact resistance, presents a Contacted-Gate-Pitch (CGP) scaling limit for …

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Effective Drive Current in Scaled FinFET and NSFET CMOS Inverters

Ali Razavieh, Yicong Deng, PETER M. ZEITZOFF, M.R. Na et autres

This work investigates the impact of CMOS scaling on the DC effective drive current,$I_{eff}$[1],$I_{eff}=1/2\times(I_{high}+I_{low})=1/2\times [d_{s}(V_{gs}=0.5V_{dd},V_{ds}=V_{dd})+(V_{gs}=V_{dd},V_{ds}=V_{dd}/2)$] of aggressively scaled MOSFETs down to 7nm node technology. FinFET and Nanosheet (NSFET) architectures [2], [3] behave similarly, and$l_{eff)}$continues to predict the intrinsic delay for aggressively scaled …

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Scaling challenges of FinFET architecture below 40nm contacted gate pitch

Ali Razavieh, PETER M. ZEITZOFF, D.E. Brown, G. Karve et autres

In addition to electrostatics challenges, FinFETs scaled below CPP of 40nm will require ρC of -8×1010Ω-cm2 if performance gains are to be extended. Attainment of ρC at fully ohmic limit, and/or innovative contact structures, will be required if FinFETs are to extend …

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A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

Ruijie Xie, Pietro Montanini, Kerem Akarvardar, Neeraj Tripathi et autres

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the …

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Extraction of parasitic and channel resistance components in FinFETs using TCAD tools

Sudarshan Narayanan, Edmund K. Banghart, PETER M. ZEITZOFF, Konstantin Korablev et autres

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Specific contact resistivity of n-type Si and Ge M-S and M-I-S contacts

Jiseok Kim, Phillip J. Oldiges, Huifeng Li, Hiroaki Niimi et autres

We have theoretically investigated the specific contact resistivity of n-type Si and Ge metal-insulator-semiconductor contacts with various insulating oxides. We have found a significant reduction of the contact resistivity for both Si and Ge with an insertion of insulators at low and …

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Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics

Bomsoo Kim, Dong-il Bae, PETER M. ZEITZOFF, Xin Sun et autres

The effect of positive fixed oxide charge (Qf) on the electrical characteristics of bulk FinFET devices is investigated and newly addressed as a Fin scaling detractor. The aggressively scaled Fin width leads to abnormal subthreshold slope (SS) degradation in nMOS devices even …

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Analysis of parasitic resistance in double gate FinFETs with different fin lengths

Xin Hui Yang, K. Maitra, Chun-Chen Yeh, PETER M. ZEITZOFF et autres

A significant increase in parasitic resistance (RPARA) fluctuation is observed when S/D length is getting smaller than the characteristic length (LTRANS). Resistance change evaluated on double gate finFETs with various fin lengths shows an excellent agreement between the experimental data and the …

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Modeling and Analysis of Parasitic Resistance in Double-Gate FinFETs

Daniel G. Tekleab, Sri Samavedam, PETER M. ZEITZOFF

A comprehensive model is presented to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width. The model incorporates the contribution of spreading, sheet, and contact resistances. The spreading resistance is modeled using a standard …

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Modeling and analysis of parasitic resistance in double gate FinFETs

Daniel G. Tekleab, PETER M. ZEITZOFF

A comprehensive model is presented to analyze the 3D source-drain resistance of undoped double gated FinFETs. The model incorporates the contribution of the spreading resistance, sheet resistance and the contact resistance. The spreading resistance is modeled using a standard 2D model generalized …

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Impact of High-κ Gate Stacks on Transport and Variability in Nano-CMOS Devices

Jeremy R. Watling, Adam R. C. Brown, Giorgio Ferrari, John R. Barker et autres

Scaling of Si MOSFETs beyond the 90 nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilising …

Monte Carlo Study of Coupled SO Scattering in Si MOSFETs with High κ- Dielectric Gate Stacks: Hot Electron and Disorder Effects

John R. Barker, Jeremy R. Watling, Andrew R. Brown, Spandan Roy et autres

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