R. Sampson

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

Q. Liu, Barbara DeSalvo, Pierre Morin, N. Loubet et autres

We report FDSOI devices with a 20nm gate length (LG) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of …

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A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

Barbara DeSalvo, Pierre Morin, Marco G. Pala, G. Ghibaudo et autres

Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the …

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10nm FINFET technology for low power and high performance applications

Dechao Guo, Huiling Shang, Keehong Seo, Bala Haran et autres

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI …

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Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

Kangguo Cheng, Soon‐Cheon Seo, Jonathan Faltermeier, Darsen D. Lu et autres

We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with …

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A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Kwangyou Seo, Bala Haran, Divya Gupta, Dechao Guo et autres

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2SRAM …

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High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

Qianlong Liu, M. Vinet, J. Gimbert, N. Loubet et autres

We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive …

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UTBB FDSOI scaling enablers for the 10nm node

L. Grenouillet, Qinrang Liu, R. Wacquez, Pierre Morin et autres

UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.

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64nm pitch interconnects: Optimized for designability, manufacturability and extendibility

Cindy Goldberg, Seong Hee Park, B. Y. Kim, Shao Beng Law et autres

In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal …

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High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

K. Cheng, Ali Khakifirooz, N. Loubet, Scott Luning et autres

For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 …

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High performance bulk planar 20nm CMOS technology for low power mobile applications

Huiling Shang, Sameer H. Jain, E. Josse, Emre Alptekin et autres

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, …

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High-K/Metal Gate MOSFETsにおける新しいレイアウト依存性(IEDM特集(先端CMOSデバイス・プロセス技術))

雅史 浜口, Deleep R. Nair, D. Jaeger, 尚志 西村 et autres

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High-K/Metal Gate MOSFETs における新しいレイアウト依存性

雅史 浜口, Deleep R. Nair, D. Jaeger, 尚志 西村 et autres

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