Emre Alptekin

Türkçe Öğretmenlerinin Web 2.0 Araçları ile Dijital Hikâye Oluşturma Yeterliği

Tuncay TÜRKBEN, Emre Alptekin

Bu araştırma, Türkçe öğretmenlerinin web 2.0 araçlarıyla dijital hikâye hazırlayıp kullanabilme yetkinlik düzeylerini belirlemeyi ve bu yetkinlikleri farklı değişkenler açısından incelemeyi amaçlamaktadır. Araştırma, tarama modellerinden ilişkisel tarama modelinde gerçekleştirilmiştir. Araştırmanın evrenini, 2021-2022 eğitim-öğretim yılında 47 farklı ilde Millî Eğitim Bakanlığına bağlı resmî …

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(Invited) Contacts in Advanced CMOS: History and Emerging Challenges

C. Lavoie, Praneet Adusumilli, Adra Carr, J. Jordan Sweet et autres

Silicide materials used as contacts in CMOS devices have evolved over many technology nodes. This article traces the often forgotten defectivity related reasons that were the primary drivers for a change in materials or process flow – evolving from Ti to Co …

(Invited) Contacts in Advanced CMOS: History and Emerging Challenges

C. Lavoie, Praneet Adusumilli, Adra Carr, J. Jordan Sweet et autres

With the continued evolution of CMOS technologies, which includes recent changes in both device geometries and contact schemes, contact lengths of advanced devices are now reaching below 20 nm. At these dimensions, material microstructure (grain size) becomes similar to contact size and …

Ti and NiPt/Ti liner silicide contacts for advanced technologies

Praneet Adusumilli, Emre Alptekin, M. Raymond, Nicolas Breil et autres

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The …

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Precleans challenges on middle-of-the-line contacts for 14nm technologies and beyond

Domingo A. Ferrer, Annie Levesque, Asli Sirman, Junedong Lee et autres

In-situ dry cleans of silicon-based surfaces preceding the metallization process step have a crucial impact on contact resistance, yield and reliability of middle-of-the-line (MOL) local interconnects. Existing precleaning techniques meet numerous challenges predominantly originated from reduced device geometries such as critical dimensions …

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Gas cluster ion beam assisted NiPt germano-silicide formation on SiGe

Ahmet S. Özcan, C. Lavoie, Emre Alptekin, Jean Jordan‐Sweet et autres

We report the formation of very uniform and smooth Ni(Pt)Si on epitaxially grown SiGe using Si gas cluster ion beam treatment after metal-rich silicide formation. The gas cluster ion implantation process was optimized to infuse Si into the metal-rich silicide layer and …

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Yabancılara Türkçe Öğretiminde Dijital Öyküleme Aracılığıyla Kültürel Ögelerin Aktarımı Transfer of Cultural Elements Through Digital Storytelling in Teaching Turkish to Foreigners

Tuncay TÜRKBEN, Emre Alptekin

Dil, anlaşma ve iletişim aracı olduğu kadar kültür taşıyıcısı ve kültür aktarım aracı olarak da işlev görmektedir.Dil ve kültür birbiriyle yakından ilişkili, birbirini bütünleyen olgulardır.Bu nedenle dil öğretimi aynı zamanda bir kültür öğretimidir.Yabancı dil öğretimi denilince de hiç kuşkusuz bir toplumun maddi …

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Understanding short channel mobility degradation by accurate external resistance decomposition and intrinsic mobility extraction

Tao Chu, Reinaldo A. Vega, Emre Alptekin, Dechao Guo et autres

An intrinsic short channel mobility extraction method is proposed by measuring two short-channel devices with different channel lengths and the same source/drain and contact geometry. The constant and dynamic components of external resistance are separated. Short-channel mobility degradation is observed and its …

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High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization

C-H. Lin, Brian J. Greene, J. Cai, A. Bryant et autres

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4thgeneration deep trench embedded DRAM …

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10nm FINFET technology for low power and high performance applications

Dechao Guo, Huiling Shang, Keehong Seo, Bala Haran et autres

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI …

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A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Kwangyou Seo, Bala Haran, Divya Gupta, Dechao Guo et autres

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2SRAM …

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Interconnect performance and scaling strategy at 7 nm node

James Hsueh-Chung Chen, Theodorus E. Standaert, Emre Alptekin, Terry A. Spooner et autres

In this paper, optimization of 1X BEOL wiring level of 7 nm node is presented. We focus on the interconnect delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on …

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