Impact of High-κ Gate Stacks on Transport and Variability in Nano-CMOS Devices

Le résumé fourni par la source

Scaling of Si MOSFETs beyond the 90 nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilising strained Si (SSi) channels. Additionally, high-kappa dielectrics are expected to replace SiO2 around or after the 45 nm node to reduce the associated gate leakage current problem, facilitating further scaling. However, in spite of significant recent technological achievements, in particular, in reducing charge trapping and crystallization of the dielectric, mobility degradation in the devices with the high-kappa gate stacks caused, in part, by the strong soft optical phonon scattering leaves room for further performance improvement. In this work we study the impact of soft optical phonon scattering on the mobility and device performance for conventional and strained Si n-MOSFETs with high-kappa dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 35 nm

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