Indira P. Seshadri

Area and Performance of Staggered-Channel Nanostack SRAM Bitcells

Chen Zhang, Carl Radens, Utkarsh Bajpai, S. Reboh et autres

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First Demonstration of a Functional Gate-All-Around Nanosheet Cmos Circuit Using Single Exposure High Na Euv Beol Interconnects

Chris Penny, Julien Frougier, Belle Antonovich, Chris Carr et autres

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Beyond scaling: high-NA EUV, EPE, and stochastic control for the age of AI

Luciana Meli, Jed H. Rankin, Indira P. Seshadri, Christopher Penny et autres

The rapid rise of AI is accelerating demand for innovations in semiconductor architecture and materials, driving the need for enhanced compute performance. Lithography remains central to this progress, enabling traditional scaling while evolving to tackle new, complex challenges. On one end, advanced …

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Evaluating three dimensionally engineered dry resist film performance for 0.33NA and High-NA EUV patterning

Saumya Gulati, Chun-Chia Brown Lu, Phil Friddle, Nizan Kenane et autres

Lam’s Aether dry resist, first introduced in 2020, offers significantly higher EUV sensitivity and lower defectivity than conventional resists—capabilities that are critical for achieving high yields at advanced technology nodes. Its precise vapor-phase deposition enables recipe-level control of film thickness, uniformity, and …

Scaling single expose EUV gate LER through source-resist-mask co-optimization

Gopal Sankar Kenath, Martin Burkhardt, Rajiv Naresh Sejpal, Yohan Seepersad et autres

Patterning stack and process co-optimization for <24P high-NA EUV lithography

Indira P. Seshadri, Christopher Penny, Zheng Chen, Nicholas Latham et autres

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Dose reduction strategies for low-n PSM absorber using pupil and mask bias optimization at 0.33NA EUV lithography

Rajiv Naresh Sejpal, Gopal Sankar Kenath, Sriharsha Sudhindra, Jed H. Rankin et autres

To maintain manufacturable low levels of defectivity and stochastics, the solutions to sub-0.5k1 patterning at Extreme Ultraviolet Lithography (EUVL) wavelength are dose (throughput) expensive. Subsequently, the lower the k1 imaging, the higher the dose required to ensure sufficient yield for high-volume manufacturing …

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Dry resist characterization towards technology insertion for 28-36P EUV patterning

Yasiel Cabrera, Gopal Sankar Kenath, Yann Mignot, Brian Conerney et autres

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Evaluating novel material stacks towards gate width roughness reduction

Gopal Sankar Kenath, Martin Burkhardt, Rajiv Naresh Sejpal, Yasiel Cabrera et autres

Gate patterning within the next generation transistor architectures have moved towards single expose EUV patterning. As the gate critical dimension and pitch scales down, there is an increasing focus on the reduction of EUV stochastics mediated effects on patterning. In particular, there …

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Accelerating high-NA EUV lithography insertion for interconnect scaling and beyond: Performance, cost, and future prospects

Luciana Meli, Indira P. Seshadri, Jed H. Rankin, Jennifer Church et autres

Dry resist patterning development towards high-NA EUV lithography

Indira P. Seshadri

An all-EUV dry resist technology offers a fundamentally new way to enable resist processing targeting differentiating capabilities for high NA lithography. Dry deposition of resists offers stochastic benefits with precise control over thickness and composition. Dry development enables in-situ tuning of development …

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EUV patterned gate variation reduction in next generation transistor architectures

Gopal Sankar Kenath, Martin Burkhardt, Nikhil Jain, Anna M. Lin et autres

Transistor architectures below the 7 nm node are significantly enabled by EUV lithography, with single exposure EUV processes simplifying small pitch patterning processes. However, EUV stochastics are a significant hurdle in meeting aggressive process assumption targets and achieving high yields. In particular, …