2025
article
OpenAlex
Weiyang Miao, Shaopeng Wang, Wang Ling Goh, Yuan Tang et autres
This study proposes a reinforcement learning (RL) framework to automate power distribution network (PDN) design in RDL interposer, such as high-density fan-out wafer-level packaging (HD-FOWLP) and CoWoS-R, for multi-chiplet systems. A four-chiplet system with a ring topology and 28 distinct power domains …
sg, fi, us, tw
(code pays fourni par la source)
2025
conference-paper
OpenAlex
Chuei-Tang Wang, Yen‐Ming Chen, Yuhuan Chen, Shu-An Shang et autres
Integrated voltage regulator (IVR) is a highly integrated power management component to provide a new solution for power supply. It can integrate complex driver ICs, high side (HS)/low side (LS) transistor, capacitors, inductors, and other components into a single die, so that …
tw
(code pays fourni par la source)
2024
conference-paper
OpenAlex
I‐Hsuan Liu, I-Ting Lin, Yueh-Feng Tsai, Jeng-Sheng Hsieh et autres
Devices empowered by Al have brought tremendous benefits to humanity. Fig. 1 shows diverse applications, such as convolutional neural network (CNN) for environmental sensing, graph convolutional network (GCN) for social network analysis, and transformer for natural language processing. Al accelerators have been …
tw
(code pays fourni par la source)
2024
conference-paper
OpenAlex
Chuei-Tang Wang, Shu-An Shang, Yu-Ming Hsiao, Mirng-Ji Lii et autres
A novel advanced packaging figure of merit (AP-FoM) for benchmarking of heterogeneous integration technology performance is proposed in this paper. The AP-FoM is composed of eye width, RC time and jitter in equation of [Eye width / (RC time*Jitter)], related to the …
tw
(code pays fourni par la source)
2023
conference-paper
OpenAlex
Chuei-Tang Wang, Shu-An Shang, Yu-Ming Hsiao, Kathy Yan et autres
CoWoS-R RDL interposer technology is a key enabling solution to provide low parasitic interconnects between chiplets for high performance computing (HPC) applications. In the study, UCIe IO circuit with data rate up to 32GT/s is implemented on the CoWoS-R technology, the solutions …
tw
(code pays fourni par la source)
2023
conference-paper
OpenAlex
Han-Jong Chia, Shih-Peng Tai, Ji James Cui, Chuei-Tang Wang et autres
The future continuation of Moore's Law will require a combination of transistor scaling as well as system scaling through the utilization of 3D chip stacking. Transistor scaling in advanced process nodes has become increasingly challenging and is projected to face difficulties in …
tw
(code pays fourni par la source)
2022
article
OpenAlex
Douglas Yu, Chuei-Tang Wang, C. S. Lin, Chih-Hsin Lu et autres
A System on Integrated Chip_Horizontal (SoIC_H) technology for heterogeneous system integration in high-performance computing (HPC) is proposed. Compute logic chiplets and memory cubes are tightly integrated on a Si interposer via ultrafine pitch SoIC bond to provide low parasitic and high density …
tw
(code pays fourni par la source)
2022
conference-paper
OpenAlex
Chuei-Tang Wang, Chia-Chai Lin, Chih-Hsin Lu, Wei‐Ting Chen et autres
An SoIC_H technology for 2.5D heterogeneous system integration is proposed. SoIC bond, replacing µbump, is used to provide low parasitic and high density of interconnects. Through system technology co-optimization (STCO), the proposed architecture provides over 60% power reduction for die-to-die I/O link …
tw
(code pays fourni par la source)
2021
conference-paper
OpenAlex
Douglas Yu, Chuei-Tang Wang, Harry Hsia
Chiplets integration technology supports Moore's law sustaining. A disruptive system integration technology platform (3DFabric™) is established to achieve the goal. There is a big room to scale up 2.5D system envelope and scale down 3D bonding pitch to provide higher system values …
tw
(code pays fourni par la source)
2020
conference-paper
OpenAlex
Shu-Rong Chun, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu et autres
A novel wafer-scale system integration solution, InFO_SoW (System-on-Wafer), has been successfully developed to integrate known-good chips arrays with power and thermal module for high performance computing. InFO_SoW eliminates the use of substrate and PCB by serving as the carrier itself. Close packed …
tw
(code pays fourni par la source)
2019
conference-paper
OpenAlex
Tzu-Chun Tang, C. S. Lin, Che‐Wei Hsu, Chun-Lin Lu et autres
High Q-factor (quality factor) 3D solenoid inductor formed by RDL (redistribution layer) and copper via in the molding compound on InFO package was fabricated. The effect of the turns and cross sectional area on Q-factor is discussed. The 3D solenoid inductor with …
tw
(code pays fourni par la source)
2019
conference-paper
OpenAlex
Chuei-Tang Wang, Douglas Yu
Novel InFO technologies have been developed to meet high bandwidth, low power consumption and small form factor requirements for system integration with key characteristics of thin dielectric layers, fine RDL lines, 3D vertical interconnects and multi-chip integration. The powerperformance advantages of the …
tw
(code pays fourni par la source)