Junmo Lee

Agentic TCAD Calibration Workflow for Oxide Semiconductor Transistors

Gyujun Jeong, Junmo Lee, Sungwon Cho, Woohyun Hwang et autres

Experimental TCAD calibration is essential for predictive technology modeling of emerging oxide semiconductor transistors. However, it remains time-consuming and expert dependent because of model ambiguity. Multiple physical models and parameter sets can reproduce the same measured transfer characteristics, while local fitting alone …

A Unified Flash Memory Platform for Mode‐Adaptive and Robust AI Computation

Dayeon Yu, Hwiho Hwang, Byeongchan Oh, Junmo Lee et autres

Computing-in-memory (CIM) architectures offer a promising route toward energy-efficient artificial intelligence by reducing data-movement overhead. However, most existing CIM hardware operates at a fixed trade-off between accuracy, energy efficiency, and robustness, limiting adaptability to diverse workloads. Here, we present a dual-mode CIM …

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Dual-Gated ALD Oxide-Channel Nonvolatile Capacitive Memory Monolithically Integrated on Foundry 40-nm CMOS for Capacitive Digital Compute-in-Memory

Junmo Lee, Chengyang Zhang, Siheon Park, H. K. Park et autres

In this work, we experimentally demonstrate monolithic 3-D (M3D) integration of dual-gated (DG) nonvolatile capacitive memory (nvCAP) featuring an ALD W-doped In2O3(IWO) channel on a foundry 40-nm CMOS chip. We introduce a novel dual-gate engineering scheme for DG nvCAP, effectively addressing the …

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Physics-Informed Neural Network-Assisted Compact Modeling for Process Variation in Non-Volatile Capacitive Crossbar Arrays

Gyujun Jeong, Jungyoun Kwak, Madhav Vadlamani, Junmo Lee et autres

Ferroelectric non-volatile capacitor (nvCAP) device is a new candidate for charge-domain computing. The impact of process variation (PV) is yet to be quantified. This work presents a physics-informed neural network (PINN)-assisted compact model that accurately captures effects under PV parameters for scaled …

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Physics-Informed Neural Network-Assisted Compact Modeling for Process Variation Analysis in Non-Volatile Capacitive Crossbar Arrays

IEEE International Symposium on Reliability Physics 2026, Gyujun Jeong, Jungyoun Kwak, Junmo Lee et autres

The impact of process variation (PV) on ferroelectric non-volatile capacitors (nvCAPs), emerging devices for charge-domain computing, is yet to be quantified. This work presents a physics-informed neural network (PINN)-assisted compact model accurately capturing PV effects in scaled nvCAPs, demonstrating superior physical accuracy …

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Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache

Faaiq Waqar, Jungyoun Kwak, Junmo Lee, Omkar Phadke et autres

The Last Level Cache (LLC) is the processor’s critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To date, high-density (HD) SRAM has been the conventional device of choice; however, with the …

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Pulse-Mode Operation and Reliability of BEOL-Compatible Ferroelectric Non-Volatile Capacitive Memories with Amorphous Oxide Semiconductor Channels

Junmo Lee, Chengyang Zhang, Tae‐Hyeon Kim, Suman Datta et autres

Non-volatile capacitive memories (nvCAPs) exhibiting AC small-signal capacitance on/off ratio (Con/Coff) with non-destructive read have emerged as a promising device for next-generation memory paradigms. Recently, BEOL-compatible ferroelectric nvCAPs with an amorphous oxide semiconductor channel have been reported, suggesting the possibility of monolithic …

Array-Level Demonstration of Charge-Domain In-Memory Search using Back-End-of-Line Compatible Ferroelectric Nonvolatile Capacitors

Omkar Phadke, Junmo Lee, Po-Kai Hsu, Chengyang Zhang et autres

In this work, we experimentally demonstrate a charge-domain Ternary Content Addressable Memory (TCAM) array using back-end-of-line (BEOL) compatible ferroelectric non-volatile capacitors (nvCAPs) for in-memory search. The TCAM cell consists of two nvCAPs to store bit ('0, 1, X), and an additional nvCAP …

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Monolithic 3D Integration of Dual-Gated ALD Oxide-Channel Non-Volatile Capacitive Memory on 40nm Si CMOS for Digital Compute-in-Memory

Junmo Lee, Chengyang Zhang, Siheon Park, Hyeonwoo Park et autres

We experimentally demonstrate monolithic 3D (M3D) integration of dual-gated (DG) non-volatile capacitive memory (nvCAP) featuring an ALD W-doped In2O3(IWO) channel on a TSMC N40 CMOS foundry chip. Key technical advancements include: i) Novel dual-gate engineering of nvCAP, effectively addressing the weak erase …

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High-Efficiency BEOL-Compatible On-Chip Switched Capacitor DC-DC Converter Using Planar and Vertical Oxide Transistors with Trench Capacitors

Sunbin Deng, Hung-Chun Chou, Chengyang Zhang, Jungyoun Kwak et autres

This work presents a breakthrough in on-chip point-of-load (PoL) DC-DC voltage conversion for heterogeneous 3D integrated circuits by leveraging BEOL-compatible transistor and trench capacitor architectures. This work presents indium-tin-oxide (ITO) planar transistors and vertical indium-gallium-oxide (IGO) transistors, achieving a specific on-resistance of …

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Machine Learning-Assisted Compact Modeling of AC Stress-Induced Bias Temperature Instability in Top- and Bottom-Gate W-Doped In₂O₃ Channel Semiconductor Transistors

Jungyoun Kwak, Sunbin Deng, Chengyang Zhang, Omkar Phadke et autres

This article presents a machine learning (ML)-assisted compact modeling framework to analyze and mitigate bias temperature instability (BTI) under alternating current (ac) stress in oxide semiconductor-channel transistors, with a focus on 2T gain cell (GC) embedded DRAM (eDRAM) applications. We investigate top-gate …

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A Comprehensive Modeling of Gate Stack Interlayer Engineering for Ferroelectric Vertical NAND

Minji Shon, Chinsung Park, Prasanna Venkatesan Ravindran, Lance Fernandes et autres

Ferroelectric field-effect transistors (FeFETs)-based vertical NAND (Fe-VNAND) has emerged as a promising solution to z-scaling limitations of conventional charge trap layer (CTL)-based VNAND (Fig. 1) with reduced programming voltage (from $\gt30 \mathrm{~V}$ to $(\lt)15 \mathrm{~V}$) [1]. Band engineered FeFETs are actively being …

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