B.J. Hwang

Highly Manufacturable 64M bit Ultra Low Power SRAM Using a Novel 3-Dimensional S3 (Stacked Single-crystal Si) Cell Technology

W.S Cho, Hoon Lim, Jae Hoon Jang, Yaopeng Kang et autres

Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology

K. Koh, B.J. Hwang, K.H. Kwak, Y.S. Son et autres

As scaling down the device, it is difficult to control the standby leakage and device performance at the same time. In this work, 6-transistor SRAM cell using buried channel PMOS technology was introduced and the device for low power consumption was analyzed. …

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Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

Young-Tae Kang, Sung Mi Jung, Jae Hoon Jang, J.H. Moon et autres

The PMOS SSTFT (stacked single-crystal thin film transistor) is developed for achieving the smallest SRAM cell size, such as 45F/sup 2/, and low power mobile applications with the single crystallization technology of the Si thin films on the insulators. The electrical properties …

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Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)

Jae Hoon Jang, S. Jung, Young-Tae Kang, W.S. Cho et autres

We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical node contacts are major keys in the S/sup 3/ cell technology. The stacked single …

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The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM

Soon‐Moon Jung, Jaehoon Jang, Wonseok Cho, Jaehwan Moon et autres

The smallest 25F/sup 2/ SRAM cell size of 0.16um/sup 2/ is realized by S/sup 3/ cell technology and SSTFT with 193nm ArF lithography process. The stacked single-crystal thin film is developed and used for the first time in the SRAM cell to …

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Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation

D.H. Kim, Seung Ju Kim, B.J. Hwang, SungYong Seo et autres

For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask …

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Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology

K. Koh, B.J. Hwang, G. H. Han, K.H. Kwak et autres

High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and 205 /spl mu/A//spl mu/m, respectively. The random access time of 17 ns at 1.65 V operation …

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Development of viscous PR flow technology for 0.26 /spl mu/m contact pitch on 0.84 /spl mu/m/sup 2/ SRAM cell [photoresist flow]

B.J. Hwang, Kyungnam Koh, Wonjun Jung, T.K. Kim et autres

The PR (photoresist) flow process for small contact patterning is difficult to predict and optimize because it is sensitively affected by the process condition, pattern density and environment as well. In this paper, a model of viscous flow by surface tension for …

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Borderless contact leakage induced standby current failure on sub-0.15 μm CMOS device

D.H. Kim, J.H. Kim, B.J. Hwang, D.Y. Cho et autres

For the downscaling of CMOS device design rules with high device performance, the reduced active area forces formation of a borderless contact in local interconnects. As the contact area is decreased with downscaling, it induces failure of device electrical characteristics and reliability. …

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