W.S. Cho

Effects of O2 addition on microstructure and electrical property for ITO films deposited with several kinds of ITO targets

S.H. Cho, J.H. Park, S.C. Lee, W.S. Cho et autres

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Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

Young-Tae Kang, Sung Mi Jung, Jae Hoon Jang, J.H. Moon et autres

The PMOS SSTFT (stacked single-crystal thin film transistor) is developed for achieving the smallest SRAM cell size, such as 45F/sup 2/, and low power mobile applications with the single crystallization technology of the Si thin films on the insulators. The electrical properties …

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Highly area efficient and cost effective double stacked S/sup 3/ (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM

Soon‐Moon Jung, N. Lim, W.S. Cho, Hoosung Cho et autres

For the first time, the highest density SRAM, such as 512M bit SRAM, is developed by implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose cell size is 0.16/spl mu/m/sup 2/, and area saving peripheral SSTFT (stacked single-crystal thin film transistor) …

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Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)

Jae Hoon Jang, S. Jung, Young-Tae Kang, W.S. Cho et autres

We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical node contacts are major keys in the S/sup 3/ cell technology. The stacked single …

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