2025
article
OpenAlex
Hyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, S.-H. Lee et autres
This paper presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining …
kr
(code pays fourni par la source)
2024
article
OpenAlex
Young-Ju Oh, Chan-Ho Lee, Sang-Yun Nam, Jun-Seok Oh et autres
This article proposes a control method for buck converter used in a highly integrated system to ensure robust operation even when the converter operates with significantly high on-duty (DON). According to the DON, the proposed controller automatically changes the operation mode between …
kr
(code pays fourni par la source)
2010
article
OpenAlex
Minho Choi, Gil‐Cho Ahn, S.-H. Lee
A 12b 50 MS/s 0.18 µm CMOS ADC with a highly linear variable gain amplifier (VGA) for medical ultrasound and CCD image sensor applications is presented. The proposed four-step pipeline ADC optimises power and chip area at target specifications while the front-end …
kr
(code pays fourni par la source)
2010
article
OpenAlex
V. Hariprasath, Jon Guerber, S.-H. Lee, Un-Ku Moon
A modified merged capacitor switching (MCS) scheme is proposed for the successive approximation register (SAR) analogue-to-digital converter (ADC). The conventional MCS technique previously applied to a pipelined ADC improves signal processing speed and, with use in the SAR ADC, this scheme achieves …
us, kr
(code pays fourni par la source)
2009
article
OpenAlex
K.-H. Lee, S.-W. Lee, Y.-J. Kim, K.-S. Kim et autres
A ten-bit (10b) 100 MS/s 0.18 µm CMOS three-step pipeline ADC with various circuit sharing techniques is described. Two MDACs share a single two-stage low-power switched amplifier without MOS series switches and memory effects as observed in conventional shared op-amps. All three …
kr
(code pays fourni par la source)
2009
article
OpenAlex
K.-H. Lee, Y.-J. Kim, K.-S. Kim, S.-H. Lee
Described is a 14 bit 50 MS/s CMOS four-stage pipeline A/D converter (ADC)-based on a digital code-error calibration. The proposed calibration technique measures the capacitor mismatch errors of the front-end multiplying DAC (MDAC) with the back-end pipeline stages while the measured code …
kr
(code pays fourni par la source)
2007
article
OpenAlex
K.-H. Lee, Hyeon-Ji Choi, Kyoung-Jun Moon, Y.-L. Kim et autres
A 14b 70MS/s pipeline A/D converter (ADC) in a 0.13 µm CMOS process employs signal insensitive 3D fully symmetric capacitors for high matching accuracy without any calibration scheme. The prototype ADC with a die area of 3.3 mm2 shows measured differential and …
kr
(code pays fourni par la source)
2006
article
OpenAlex
S.-C. Lee, K.-D. Kim, Jae Kyun Kwon, Jungsoo Kim et autres
This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the …
kr
(code pays fourni par la source)