Radar System-in-Package with Integrated Antennas based on Fan-Out Wafer-Level Packaging RDL-First Integration
Arnaud Garnier, Laetitia Castagné, Jean-Charles Souriau, Rémi Franiatte et autres
0 citations
Laetitia Castagné
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24Publications signalées
86Citations signalées
4Affiliations récentes
Institutions déclarées
Domaines associés
3D IC and TSV technologiesElectronic Packaging and Soldering TechnologiesAdditive Manufacturing and 3D Printing TechnologiesAdvanced Sensor and Energy Harvesting MaterialsSemiconductor materials and devices
Publications récentes
Advancing Fan-Out Wafer-Level Packaging for III-V/CMOS Optoelectronic Transceiver SiP Integration
P. Coudrain, Laetitia Castagné, Arnaud Garnier, R. Eleouet et autres
0 citations
Characterization of Chip-to-Wafer Interconnects with Thick Gold Finish for Fan-Out Wafer-Level Packaging RDL-First Integration
Arnaud Garnier, Laetitia Castagné, Guenaëlle Massignac, Rémi Franiatte et autres
1 citation
Comparative Life Cycle Analysis of Redistribution Layer for 3D Integrations
Suzanne Guillou, D. Saint-Patrice, Laura Vauche, Laetitia Castagné et autres
1 citation
Comparative Life Cycle Assessment (LCA) of redistribution layers for 3D integration
Suzanne Guillou, D. Saint-Patrice, Laura Vauche, Laetitia Castagné et autres
0 citationsHAL (Le Centre pour la Communication Scientifique Directe)
Aging Behaviour and Environmental Impact of Under Bump Metallurgies for Wafer Level Balling
Arnaud Garnier, Laetitia Castagné, S. Moreau, Alexandra Fraczkiewicz et autres
2 citations
Flexible Hybrid Electronics Including Ultrathin Strain Sensors or Radio Frequency Identification Dies Manufactured on Wafer Silicon Carrier
Jean-Charles Souriau, Christophe Poulain, Laetitia Castagné, Carine Ladner et autres
6 citationsIEEE Transactions on Components Packaging and Manufacturing Technology
(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems
P. Coudrain, Arnaud Garnier, Laetitia Castagné, A. Plihon et autres
1 citationECS Meeting Abstracts
(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems
P. Coudrain, Arnaud Garnier, Laetitia Castagné, A. Plihon et autres
4 citationsECS Transactions
System in package embedding III-V chips by fan-out wafer-level packaging for RF applications
Arnaud Garnier, Laetitia Castagné, F. Greco, Thomas Guillemet et autres
22 citations
Flexible Fan-Out Wafer Level Packaging of Ultra-Thin Dies
Jean-Charles Souriau, Laetitia Castagné, Carine Ladner, Rémi Franiatte et autres
2 citations
Wafer Level Integration of Thin Silicon Bare Dies Within Flexible Label
Jean-Charles Souriau, Ahmad Itawi, Laetitia Castagné
3 citations
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