Comparative Life Cycle Analysis of Redistribution Layer for 3D Integrations

Résumé fourni par la source

Semiconductor packaging establishes the electrical interconnections between several chips, making it an entry point to eco-design and to consider reparability and chip reuse. The aim of this study is to provide engineers with tools for selecting processes based on environmental criteria. To do so, environmental impacts of eight different integrations for the manufacturing of 3D backside redistribution layer, located between the interposer and the solder ball enabling connection with the substrate, have been compared. Various technological processes and materials are considered: Al or Cu conductive materials, mineral or polymer insulators and physical vapor deposition or electrochemical deposition processes for the under bump metallization (UBM). The environmental impacts are evaluated using cradle-to-gate life cycle assessment methodology. The results highlight the impact of gold use, in particular on the depletion of mineral resources. Our modelling identified an eco-designed integration with a 48-76 % reduction in environmental impact compared to industry-standard scenarios, and robustness results with less than 10% variation in sheet resistance after unbiased Highly Accelerated Stress Test (uHAST) and Temperature Cycling Test (TCT).

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.