Th. Nirschl

Fabrication, optimization and application of complementary Multiple-Gate Tunneling FETs

Michael Fulde, Alexander Heigl, Mirjam Weis, Martin Wirnshofer et autres

We present fabrication, optimization and application aspects of complementary Multiple-Gate Tunneling FETs (MuGTFETs). Tunneling FETs are implemented in a MuGFET technology for the first time. N- and p-type tunneling currents are observed within a single device structure. Digital and analog device performance …

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Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

Th. Nirschl, C.-F. Chen, Eric A. Joseph, M. Lamorey et autres

We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4 bits/cell and a 32 kb memory page at 2 …

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Novel Lithography-Independent Pore Phase Change Memory

M. Breitwisch, Th. Nirschl, C.F. Chen, Yu Zhu et autres

We have successfully demonstrated a novel "pore" phase change memory cell, whose critical dimension (CD) is independent of lithography. Instead, the pore diameter is accurately defined by intentionally creating a "keyhole" with conformal deposition. Fully integrated 256 kbit test chips have been …

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Correction to "Revision of Tunneling Field-Effect Transistor in Standard CMOS Technologies"

Th. Nirschl, Mirjam Weis, Michael Fulde, Doris Schmitt‐Landsiedel

Previously published results by the authors, from 2004 to 2006, on the tunneling field-effect transistor (TFET) are revised in this correction. The devices that they had characterized as TFETs contain a conducting path in parallel to the intended tunneling junction. Therefore, the …

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Ultra-Thin Phase-Change Bridge Memory Device Using GeSb

Y. C. Chen, Charles T. Rettner, Simone Raoux, Geoffrey W. Burr et autres

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention

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Impact of process parameter variations on the energy dissipation in adiabatic logic

Juergen Fischer, Ettore Amirante, Th. Nirschl, Philip Teichmann et autres

Adiabatic logic offers high energy savings compared to standard CMOS at moderate operating speeds. Until now, only rudimentary investigations of the robustness of adiabatic circuits were presented. However, in deep sub-micron technologies the deviation of the device parameters from their nominal value …

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Modelling of the parametric yield in decananometer SRAM-Arrays

Thomas M. Fischer, Th. Nirschl, B. Lemaitre, Doris Schmitt‐Landsiedel

Abstract. In today's decananometer (90 nm, 65 nm, ...), CMOS technologies variations of device parameters play an ever more important role. Due to the demand for low leakage systems, supply voltage is decreased on one hand and the transistor threshold voltage is …

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Dynamic State-Retention Flip-Flop for Fine-Grained Power Gating With Small Design and Power Overhead

Stephan Henzler, Georg Georgakos, Matthias Eireiner, Th. Nirschl et autres

Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, …

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Novel One-Mask Self-Heating Pillar Phase Change Memory

Thomas D. Happ, S.H. Chen, C.F. Chen, Eric A. Joseph et autres

A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level …

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Circuit design issues in multi-gate FET CMOS technologies

Christian Pacha, K. von Arnim, T. Schulz, Weize W. Xiong et autres

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves …

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Scaling properties of the tunneling field effect transistor (TFET): Device and circuit

Th. Nirschl, St. Henzler, Juergen Fischer, Michael Fulde et autres

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The 65nm tunneling field effect transistor (TFET) 0.68μm/sup 2/ 6T memory cell and multi-V/sub th/ device

Th. Nirschl, St. Henzler, Juergen Fischer, A. Bargagli-Stoffi et autres

The tunneling field effect transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550/spl mu/A//spl mu/m which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area …

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