Chun‐Jen Su

Corrigendum to “Mesomorphic phases of the electrostatic complexes of amphiphilic surfactants with low-generation dendrimers” [Giant, 25 (2025) 100369]

Yicheng Lai, Chun-Yu Chen, Chun‐Jen Su, Hsin‐Lung Chen

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Mesomorphic Phases of the Electrostatic Complexes of Amphiphilic Surfactants with Low-Generation Dendrimers

Yicheng Lai, Chun-Yu Chen, Chun‐Jen Su, Hsin‐Lung Chen

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Design and modeling of PLL-based clock and data recovery circuits with periodically embedded clock encoding for intra-panel interfaces

Hsi‐En Liu, Chun‐Jen Su, Chih‐Kang Cheng, Wen‐Kuen Liu

This study investigates the design issues of a phase-locked loop (PLL)-based point-to-point (P2P) high-speed interface with periodically embedded clock encoding (PECE). Interfaces of this type are the mainstream serial links for 4K2K or higher resolution applications in the display industry. Early works …

P‐39: High Speed and Power‐Saving Interface for High‐Resolution and Low Power Display Panel

Hsi‐En Liu, Chun‐Jen Su, Chih‐Kang Cheng, Wen‐Kuen Liu

An 8‐bit, 1446‐channel source driver IC for the 2K resolution application has been presented. The proposed source IC adopts the point‐to‐point (P2P) interface with the embedded clock to achieve the high video data rate requirement. The fine‐grained control has also been developed …

Sub-sampling charge pump and random pulsewidth matching technique for frequency synthesizer

Te-Wen Liao, Chun‐Jen Su, Chung-Chih Hung

This paper presents a frequency synthesizer system with random pulsewidth matching technique and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage …

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Ring-VCO based low noise and low spur frequency synthesizer

Te-Wen Liao, Chun‐Jen Su, Chung-Chih Hung

This paper presents a low phase-noise phase locked loop (PLL) system with a Multi-Phase Over-Sampling Charge Pump (MPOSCP) for wireless applications. The low phase-noise frequency synthesizer reduces ripples and noise on the control voltage of the ring voltage-controlled oscillator (VCO) as a …

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Delay-line based fast-locking all-digital pulsewidth-control circuit with programmable duty cycle

Chun‐Jen Su, Te-Wen Liao, Chung-Chih Hung

This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty-cycle. In comparison with prior art, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while …

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Random Pulsewidth Matching Frequency Synthesizer With Sub-Sampling Charge Pump

Te-Wen Liao, Chia-Min Chen, Chun‐Jen Su, Chung-Chih Hung

This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce …

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Low-spur technique for Integer-N phase-locked loop

Te-Wen Liao, Chun‐Jen Su, Chung-Chih Hung

In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output …

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All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle

Chun‐Jen Su, Te-Wen Liao, Chung-Chih Hung

This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty cycle. In comparison with prior state-of-the-art methods, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay …

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Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD

Te-Wen Liao, Chun‐Jen Su, Chung-Chih Hung

This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random …

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A low-noise wide range delta-sigma frequency synthesizer for DTV broadband

Te-Wen Liao, Chun‐Jen Su, Chung-Chih Hung

The proposed low noise wide frequency range Phase Loco Loop (PLL) proposed in TSMC 0.18-um CMOS technology is developed for DTV broadband. It incorporates a Extended Multi-band Ring Voltage Control Oscillator (VCO) to enhance the frequency selection range of the conventional Multi-band …

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