Evaluation of Worst-Case Power-Delay Performance for a 1-Bit Full Adder
Pallavi G. Darji, Devansh Makwana, Arpita Patel, Purvang D. Dalal et autres
The growing demand for high-performance computing requires the development of compact, high-speed, and energy-efficient processor architectures. As a critical component within Arithmetic Logic Units(ALUs) and Floating-Point Units (FPUs), the full adder significantly impacts overall system performance and power efficiency. This study investigates …
in (code pays fourni par la source)
1 citation