Evaluation of Worst-Case Power-Delay Performance for a 1-Bit Full Adder

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The growing demand for high-performance computing requires the development of compact, high-speed, and energy-efficient processor architectures. As a critical component within Arithmetic Logic Units(ALUs) and Floating-Point Units (FPUs), the full adder significantly impacts overall system performance and power efficiency. This study investigates and evaluates various full-adder implementations that utilize 90-nm CMOS technology within the Virtuoso Cadence EDA tool. A comprehensive testing methodology was used, which encompassed all 56 possible input combinations and nine distinct input patterns, to determine the worst-case delay and maximum dynamic power dissipation. Furthermore, the study analyzed the influence of temperature variations and capacitive loading on delay and power consumption, providing valuable insights into the full adder’s performance across diverse operating conditions. The 28T Full-Adder demonstrated superior performance, while the 28T Multiplex-based Full Adder exhibited the lowest performance among the four architectures evaluated.

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