Glen D. Wilk

3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography

Shake Karapetyan, Steven Eric Zeltmann, Glen D. Wilk, Ta-Kun Chen et autres

Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale metrology to identify and resolve performance-limiting fabrication challenges. X-ray methods provide 3D information but lack atomic resolution, while conventional electron microscopy offers …

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3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography

Shake Karapetyan, Steven E. Zeltmann, G. D. Wilk, Ta-Kun Chen et autres

Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale metrology to identify and resolve performance-limiting fabrication challenges. X-ray methods provide 3D information but lack atomic resolution, while conventional electron microscopy offers …

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Atomic Layer Deposited Amorphous Ge-Doped Indium Oxide with Enhanced Mobility-Stability-Crystallization Resistance Tradeoff

Yushan Lee, Xingtian Wang, Jiahui Duan, Guanyu Zhou et autres

In this work, we demonstrate the potential of germanium-doped indium oxide (Ge:In2O3) as a promising oxide semiconductor offering an improved tradeoff among mobility, electrical stability, and crystallization resistance. This makes it suitable for both500 °C 1T1C DRAM process. Through a comparative study …

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3D Imaging of Defects, Buried Interfaces, and Strain with Multislice Electron Ptychography

Shake Karapetyan, Steven Eric Zeltmann, Prosun Santra, Malcolm G. Thomas et autres

As devices continue to shrink, precise control over atomic-scale structures – such as dopant placement, interface roughness, and other critical structural features – becomes increasingly critical for optimizing performance in both classical and quantum computing applications. Achieving reliable, dose-efficient 3D visualization of …

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First Demonstration of BEOL Wafer-Scale All-ALD Channel CFETs Using IGZO and Te for Monolithic 3D Integration

Chang Lei Niu, Pukun Tan, Jian-Yu Lin, Linjia Long et autres

In this work, we demonstrated for the first time Back-End-Of-Line (BEOL) compatible complementary field-effect transistors (CFETs) with wafer-scale all atomic-layer-deposited (ALD) channels for monolithic 3D integration. A p-type transistor based on Tellurium (Te)/Tellurium oxide (TeOx) heterostructure was fabricated on top of an …

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Wafer-Scale Atomic Layer-Deposited TeOx/Te Heterostructure P-Type Thin-Film Transistors

Pukun Tan, Chang Lei Niu, Zehao Lin, Jian-Yu Lin et autres

There is an increasing demand for p-type semiconductors with scalable growth, excellent device performance, and back-end-of-line (BEOL) compatibility. Recently, tellurium (Te) has emerged as a promising candidate due to its appealing electrical properties and potential low-temperature production. So far, nearly all of …

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Exploring the limits of transistor scaling with electron microscopy

David Anthony Muller, Frieder H. Baumann, Paul M. Voyles, Glen D. Wilk

The smallest features on transistors used in computer circuits have approached atomic dimensions: the silicon dioxide gate oxides are between 5 and 8 silicon atoms thick and the concentration of dopant atoms has increased to the point that electrically inactive dopant clusters …

(Invited) Current Status of High-k and Metal Gates in CMOS

Glen D. Wilk, Mohith Verghese, Peijun Chen, Jan Willem Maes

Continued scaling of microelectronic devices has driven the change from SiO2 to alternative, Hf-based, high-k gate dielectric materials in recent years. This materials change has enabled device performance scaling without the gate leakage current becoming unacceptably high. The change from doped poly-Si …

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Current Status of High-k and Metal Gates in CMOS

Glen D. Wilk, Mohith Verghese, Peijun Chen, Jan Willem Maes

Abstract not Available.

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Processing and Characterization of III–V Compound Semiconductor MOSFETs Using Atomic Layer Deposited Gate Dielectrics

P. D. Ye, Glen D. Wilk, Martin M. Frank

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Atomic layer deposited TaCy metal gates: Impact on microstructure, electrical properties, and work function on HfO2 high-k dielectrics

Dina H. Triyoso, Rich Gregory, Jamie K. Schaeffer, Dennis Werho et autres

TaC y has been reported to have the appropriate work function for negative metal-oxide semiconductor metal in high-k metal-oxide field-effect transistors. As device size continues to shrink, a conformal deposition for metal gate electrodes is needed. In this work, we report on …

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Impact of Hf-Precursor Choice on Scaling and Performance of High-k Gate Dielectrics

Jan Willem Maes, Yanina Fedorenko, Annelies Delabie, Lars‐Aåke Ragnarsson et autres

Downscaling of CMOS gate stacks requires introduction of ultra-thin high-k dielectrics such as HfO2. Atomic Layer Deposition has excellent characteristics for depositing such films. We have compared HfCl4/H2O and TEMAH/O3 ALD between 245ºC and 370ºC. Growth behavior and electrical performance are discussed …

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