Jifang Jin

A scalable hybrid architecture for high performance data-parallel applications

Moucheng Yang, Jifang Jin, Zhehao Li, Xuegong Zhou et autres

This paper presents a scalable hybrid architecture for high performance data-parallel applications on tightly coupled shared-memory CPU-FPGA systems such as the Xilinx Zynq SoC. The aims of the proposed architecture are: 1)to simplify the development of hardware acceleration for dataparallel applications; 2)to …

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A moving object extraction and classification system based on Zynq and IBM SuperVessel

Zhehao Li, Jifang Jin, Lingli Wang, Ji Yang et autres

In this demonstration, we develop a moving object extraction and classification system based on a heterogeneous acceleration platform that consists of a local Zynq terminal and FPGA clusters on the IBM SuperVessel cloud. Extraction of the moving object from the streaming video …

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High-performance K-means Implementation based on a Coarse-grained Map-Reduce Architecture.

Zhehao Li, Jifang Jin, Lingli Wang

High-performance K-means Implementation based on a Simplified Map-Reduce Architecture

Zhehao Li, Jifang Jin, Lingli Wang

The k-means algorithm is one of the most common clustering algorithms and widely used in data mining and pattern recognition. The increasing computational requirement of big data applications makes hardware acceleration for the k-means algorithm necessary. In this paper, a simplified Map-Reduce …

K-nearest neighbor algorithm implementation on FPGA using high level synthesis

Zhehao Li, Jifang Jin, Xuegong Zhou, Zhihua Feng

The K-Nearest Neighbor (K-NN) algorithm is one of the most common classification algorithms and widely used in pattern recognition and data mining. K-NN hardware acceleration is necessary for applications with massive high-dimensional data. High level synthesis (HLS) is an increasingly adopted technique …

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An adaptive cross-layer fault recovery solution for reconfigurable SoCs

Jifang Jin, Jian Jun Yan, Xuegong Zhou, Lingli Wang

Due to the technology scaling, the reconfigurable SoCs built on SRAM-based FPGAs become more susceptible to radiation and aging effects. This paper proposes an adaptive cross-layer fault recovery solution based on hardware/software co-design for reconfigurable SoCs. By pyramidal structure design and cross-layer …

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UniStream: A unified stream architecture combining configuration and data processing

Jian Jun Yan, Jifang Jin, Ying Wang, Xuegong Zhou et autres

This paper proposes UniStream, a unified stream architecture based on point-to-point stream channels combining both bitstream configuration and data stream processing. In addition, unified APIs are provided to support bitstream configuration and data stream processing, as well as the stream interconnect. A …

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