Erdem Kaltalioglu

Novel mmWave NMOS Device for High Pout mmWave Power Amplifiers in 45RFSOI

Sameer H. Jain, Dimitri C. Lederer, Arvind Kumar, Sudesh Saroop et autres

The adoption of 5G mmWave is upon us, with major cell phone companies having introduced phones with mmWave capabilities and major US cellphone providers building their infrastructure out. Parts manufactured using Globalfoundries 45RFSOI technology have made significant traction in the infrastructure space. …

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Thermal Characterization and TCAD Modeling of a Power Amplifier in 45RFSOI for 5G mmWave Applications

Peter Paliwoda, Mohamed A. Rabie, Oscar D. Restrepo, Erdem Kaltalioglu et autres

This paper presents a systematic methodology by thermal characterization and simulation of a 3-FET stacked K/Ka-band class-AB power amplifier built on GLOBALFOUNDRIES 45nm SOI process. A detailed temperature profile is obtained in the FEOL and BEOL stacks by first using special gate …

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Impact of oxygen plasma on nitrided and annealed atomic layer deposited SiO2/high-k/metal gate for high-voltage input and output fin-shaped field effect transistor devices

Shahab Siddiqui, Min Dai, Rainer Loesing, Erdem Kaltalioglu et autres

In this study, the authors investigate the impact of radical oxygen plasma on nitrided and annealed atomic layer deposited (ALD) SiO2 as a thick gate oxide (1.65–3 V) with a high-k/metal gate transistor. Time-dependent-dielectric-breakdown voltage, secondary ion mass spectroscopy (SIMS), and x-ray …

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64nm pitch interconnects: Optimized for designability, manufacturability and extendibility

Cindy Goldberg, Seong Hee Park, B. Y. Kim, Shao Beng Law et autres

In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal …

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Competitive and cost effective copper/low-k interconnect (BEOL) for 28nm CMOS technologies

R. A. Augur, Craig Child, Jung-Joon Ahn, Teck Jung Tang et autres

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Reliability Challenges in Copper Metallizations arising with the PVD Resputter Liner Engineering for 65nm and Beyond

A. Fischer, Oliver Aubel, Jason Gill, T.C. Lee et autres

In this paper the influence of liner deposition parameters on the reliability of 65nm copper metallizations have been investigated for two different deposition sequences. The use of resputter liners in the 65nm generation turned out to change the via-voiding failure mode qualitatively …

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65nm cmos technology for low power applications

An Steegen, Rongcheng Mo, Randy W. Mann, Min Sun et autres

This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2and 0.54mum2SRAM cells, …

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A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

S. Sankaran, S. Arai, R. A. Augur, Mattias Beck et autres

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led …

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Reliability Characterization of BEOL Vertical Natural Capacitor using Copper and Low-k SiCOH Dielectric for 65nm RF and Mixed-Signal Applications

F. Chen, F. Ungar, A. Fischer, Jason Gill et autres

Integration of low-cost and high performance passive capacitors into existing Silicon CMOS technologies is essential for analog and radio frequency (RF) IC applications. Recently, BEOL vertical natural capacitors (VNCAP) with stacked via-comb structures have emerged as an attractive option due to their …

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High performance and low power transistors integrated in 65nm bulk CMOS technology

Zuying Luo, An Steegen, Manfred Eller, Randy W. Mann et autres

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed …

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Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology

T. Schafbauer, J. Brighten, Yi-Cheng Chen, L. A. Clevenger et autres

Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low …

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A 0.13 μm CMOS platform with Cu/low-k interconnects for system on chip applications

T. Schiml, S. Biesemans, G. Brase, Lloyd G. Burrell et autres

We describe an advanced 0.13 /spl mu/m CMOS technology platform optimized for density, performance, low power and analog/mixed signal applications. Up to 8 levels of copper interconnect with the industry's first true low-k dielectric (SiLK, k=2.7) (Goldblatt et al., 2000) result in …

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