Kung‐Yen Lee

Annealing ambient engineering for tuning forward conduction and reverse blocking in Ni/(Al0.4Ga0.6)2O3/4H-SiC heterojunction diodes

Minseok Kim, Chowdam Venkata Prasad, Hyeon-Do Kang, Jin-Woo Choi et autres

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Impact of Source Contact Segmentation on the Electrical Characteristics of 4H‐SiC Planar MOSFETs

Jui-Chi Chu, Yu‐Ying Li, Pei-Chi Liao, Kung‐Yen Lee et autres

Source contact (SC) segmentation is investigated as a layout approach for tuning the capacitance, conduction, blocking, and switching characteristics of 1.7 kV 4H‐silicon carbide (4H‐SiC) planar metal‐oxide‐semiconductor field‐effect transistors (MOSFETs). Three‐dimensional TCAD simulations and measurements of fabricated small and large area devices …

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Effects of post-deposition annealing ambient on the electrical and chemical properties of ZnO/4H-SiC heterojunction diodes

Chang-Jun Park, Chowdam Venkata Prasad, MINSEOK KIM, Jin-Woo Choi et autres

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Short-Circuit Reliability Analysis of SG-MOSFETs vs Planar 4H-SiC MOSFETs

Pei Chun Liao, Kung‐Yen Lee, Ruei Ci Wu, Yan Yu Wen et autres

This work investigates the short-circuit (SC) reliability of Split-Gate (SG) versus planar 4H-SiC MOSFETs through TCAD simulations. While SG-MOSFETs effectively reduce gate-drain capacitance and improve switching performance, SG-MOSFETs exhibit enhanced short-circuit failure effects. Structural optimization—such as thicker drift regions, extended gate lengths, …

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Influence of Cell Structure and Topology on Coss of 4H-SiC MOSFET

Ruei Ci Wu, Kung‐Yen Lee, Pei Chi Liao, Pei Chun Liao et autres

This study demonstrates that the output capacitance ( C oss ) of a 4H-SiC MOSFET is proportional to the length of JFET ( L JFET ) at a low V ds , since under this condition, the gate-to-drain capacitance ( C gd …

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A Novel 4H-SiC Edge Termination Structure Using Double-Implanted P-Well and N +

Jui-Chi Chu, Wei-Xiang Wang, Kung‐Yen Lee, Ruei-Chi Wu et autres

This work proposes and validates a novel DIPN (Double-Implanted P-well and N+) edge termination for 1.7 kV-class 4H-SiC power devices. TCAD simulated and measured results demonstrate that inserting shallow N+regions inside each P-well ring forms a multi-peak electric-field profile, effectively reducing the …

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Surface engineering of p-Cu2O for enhanced hole injection in p-Cu2O/β-Ga2O3 heterojunctions

Minseok Kim, Chowdam Venkata Prasad, Seung-Hyun Park, Jin-Woo Choi et autres

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Temperature-dependent electrical analysis of SnO2/4H-SiC Schottky diodes: role of post-deposition annealing

Chang-Jun Park, Chowdam Venkata Prasad, Yejin Kim, Seunghyun Park et autres

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Short-Circuit Characterization of a Planar 1200 V SiC MOSFET by TCAD Electro-Thermal Modeling

Pei-Chi Liao, Xuan Hu, Yi-Pin Lee, Kung‐Yen Lee et autres

The short-circuit (SC) reliability is critical for SiC MOSFETs in high-power systems, as excessive current and voltage may trigger the parasitic BJT and cause device failure. A 1200 V planar SiC MOSFET was analyzed using calibrated TCAD electro-thermal simulations. The influence of …

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Analysis of ESD capability of SiC MOSFET with various cell designs

Jianjie Chen, Kung‐Yen Lee, Wei Fu, Ruei-Ci Wu et autres

Abstract The electrostatic discharge (ESD) test is conducted to evaluate the reliability of metal oxide semiconductor field effect transistors (MOSFETs). When an ESD pulse is applied to the MOSFET, excessive ESD energy can damage the device when the energy is not dissipated …

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Surface Engineering of p-Cu2O for Enhanced Hole Injection in p-Cu2O/β-Ga2O3 Heterojunctions

Minseok Kim, Chowdam Venkata Prasad, Seunghyun Park, Jin‐Woo Choi et autres

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Adjustment of Abrupt Drops in the C-V Curves of Various 4H-SiC MOSFETs and JBS Diodes

Ruei-Ci Wu, Kung‐Yen Lee, Pei‐Chun Liao

This study demonstrates the corresponding voltages to the abrupt drops in the C-V curves of the planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and junction barrier Schottky (JBS) diodes without the P-pillar can be adjusted by designing the concentrations and structures of P-type regions, …

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