Channel-Side Interlayer Engineering in Laminated FeFETs: Trap-Driven Optimization of Memory Window, Retention, and Disturb in Ferroelectric NAND Flash

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We demonstrate that laminated FeFETs for Fe-NAND exhibit a distinct channel-side interlayer (C-IL) behavior: low-k SiO2 delivers superior memory window, retention, and pass-disturb reliability compared to high-k Al2O3 and HfO2. Experiments and TCAD reveal that although high-k C-ILs lower EOT, their higher trap densities induce MW narrowing, faster retention loss, and stronger electron trapping. These findings highlight C-IL trap engineering as a key enabler for reliable, high-density Fe-NAND and clarify how C-IL traps govern reliability.

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