R. K. Sharma

Visualization-Guided Debug Methodology for Verification of GPU Fixed-Function Pipelines Under Stall Scenarios

Chirag Tripathi, R. K. Sharma

in (code pays fourni par la source)

FPGA-Based Digital Control Architecture for Single-Axis Solar Tracking System

Shaik Famida, R. K. Sharma

in (code pays fourni par la source)

A Lightweight Hybrid DVFS Governor with EMA Smoothing and Asymmetric Hysteresis: FPGA Based Evaluation and Node-Scaled Analysis

Chirag Tripathi, R. K. Sharma

Dynamic Voltage and Frequency Scaling (DVFS) continues to be a core method of performance and power adaptation of digital systems. However, the conventional DVFS governors which only rely on instantaneous workload measurements often have mode-chattering, unstable transitions, and cannot handle bursty loads. …

in (code pays fourni par la source)

P0788 Risk factors for adverse pathology in biopsy Gleason 3+4 prostate cancer: Refining criteria for safe active surveillance

Y. Ozawa, C.M. Marcio, R. K. Sharma, M. Sandri et autres

P0174 Prospective validation of a 10-point prognostic model in RCC With IVC tumor thrombus: Thrombus level does not predict survival

V. Meyyappan, R. K. Sharma, A. Mohan, P. Balagangatharan et autres

A0268 Reassessing prognosis in RCC with venous tumor thrombus: Prospective cohort study from 46 cases

V. Meyyappan, R. K. Sharma, A. Mohan, P. Balagangatharan et autres

P0237 Comparison of stent related symptoms between regular double-J stent versus Comfi-J stent: A single blinded randomized control trial

A. Shrestha, A.K. Shah, B. Adhikari, U. Mishra et autres

Real Time Dynamic AES-256 Key Generation Using DWT Coefficients and Lightweight SHA-Inspired KDF for Secure Embedded Systems

Vetcha Venkat Bhargav, R. K. Sharma

Real time encryption systems need to be able to handle a lot of data and have a lot of different keys. This is especially true for growing edge security, IoT, and audio applications. But traditional AES implementations use keys that don’t change …

in (code pays fourni par la source)

Design, Implementation, and Analysis of 64-bit Hybrid Adders Using Carry Look-Ahead and Carry Select Techniques on FPGA

Gouthami Valigonda, R. K. Sharma

This project focuses on the design, implementation, and analysis of various 64-bit adder architectures using Verilog, targeting the Xilinx Artix-7 FPGA. Three distinct types of adders were developed: a conventional 64-bit Ripple Carry Adder (RCA), a 64-bit Carry Look ahead Ripple carry …

in (code pays fourni par la source)

False blockage: colonic dilation from Parkinson's masquerading as obstruction

B Woodbeck, S Parekh, R. Jegadeesh Kumar, Y Santharam et autres

Atypical hallucinations in Kawasaki disease mimicking multisystem inflammatory syndrome in children in a 10-year-old male

A Lapointe, C Stokes, S Sarkar, N Mark-Borno et autres

List of contributors

Houssam Eddine Abdellatif, Adeel Arshad, Kalidasan B., Ahmed Belaadi et autres