A Lightweight Hybrid DVFS Governor with EMA Smoothing and Asymmetric Hysteresis: FPGA Based Evaluation and Node-Scaled Analysis

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Dynamic Voltage and Frequency Scaling (DVFS) continues to be a core method of performance and power adaptation of digital systems. However, the conventional DVFS governors which only rely on instantaneous workload measurements often have mode-chattering, unstable transitions, and cannot handle bursty loads. This paper presents a lightweight hybrid DVFS governor that applies an Exponential Moving Average (EMA) smoothing filter with an asymmetric hysteresis mechanism to achieve improved transition stability while maintaining hardware simplicity.The hybrid governor is evaluated using an FPGA-targeted Vivado flow for a Xilinx Artix-7 device and compared with a baseline threshold-based controller with the same workload stimuli. Experiments indicate that the hybrid governor decreases mode switches by 28%, which results in a more stable and smoother DVFS operation. Due to the static-power dominated nature of 28 nm FPGAs, it causes the total power to be almost constant (0.093-0.094 W), but dynamic power marginally grows with the additional arithmetic units. The technology-scaled power model to test its extrapolation to larger models than FPGA is built over 180 nm, 90 nm and 65 nm CMOS nodes, and demonstrates that the hybrid governor has definite dynamic power advantages in older node products or larger SoCs where transition cost is dominant. The proposed approach therefore provides a low-overhead DVFS solution for embedded processors, microcontrollers, and FPGA-based compute platforms.

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