Zuow-Zun Chen

DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers

Zuow-Zun Chen, Yen‐Cheng Kuan, Yilei Li, Boyu Hu et autres

In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained …

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A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology

Yan Zhao, Zuow-Zun Chen, Yuan Du, Yilei Li et autres

This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and …

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Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers

Zuow-Zun Chen, Yilei Li, Yen‐Cheng Kuan, Boyu Hu et autres

A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver …

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A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS

Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong et autres

A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts …

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An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

Boyu Hu, Fengbo Ren, Zuow-Zun Chen, Xicheng Jiang et autres

This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up …

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2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and −74dBc/Hz phase noise at 1MHz offset in 65nm CMOS

Yan Zhao, Zuow-Zun Chen, Gabriel L. Virbila, Yinuo Xu et autres

Spectra from 0.5 to 0.6THz play critical roles in planetary science, astrophysics and radio-astronomy as various chemical species including water, nitrates (NO2, N2O, NH3) and organics (CH4and HCN) can either absorb or reflect radiation in this frequency regime. Accordingly, NASA and ESA …

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28nm CMOSにおけるPAM16/256‐QAMとチャネル応答検出を可能にする転送クロックを用いた16Gb/s14.7mW3バンド認知シリアルリンク送信機【Powered by NICT】

Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong et autres

The Reduction and Cancellation of Phase Noise in Digital Frequency Synthesizers and Quadrature Receivers

Zuow-Zun Chen

Circuit and system techniques for reducing phase noise in frequency synthesizers, and cancelling phase noise effect in quadrature receivers are presented. Phase noise performance of digital phase-locked loops (PLLs) is limited by the time resolution of time-to-digital converters (TDC). In contrast to …

6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices

Li Du, Yan Zhang, Frank Hsiao, Adrian J. Tang et autres

Contactless (3D) touch sensors, when integrated with displays, offer many advantages over that of conventional touch-panel screens by offering a more hygienic and a more immersive & interactive human/machine interface for 3D user experiences [1]. While significant progress has been made in …

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14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB

Zuow-Zun Chen, Yen‐Hsiang Wang, Jaewook Shin, Yan Zhao et autres

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal …

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The Design and Analysis of Dual-Delay-Path

Zuow-Zun Chen, Tai‐Cheng Lee

A dual-operation-mode ring oscillator that employs dual-delay paths is presented. The two operation modes, referred to as the differential and common modes, have different output waveform characteristics and oscillation frequencies. A nonlinear model for the dual-delay-path ring oscillator and the analysis of …

A Multiphase Compensation Method with Dynamic Element Matching Technique in Σ-Δ Fractional-N Frequency Synthesizers

Zuow-Zun Chen, Tai‐Cheng Lee

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a Σ-? fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on Σ-? quantizetion noise. In the delay …