Demonstration of a novel double shielding and current spreading SiC trench MOSFET with high robustness

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In this paper, a novel SiC trench MOSFET structure is proposed, featuring deeply implanted P+ shielding regions on both sides of the trench (P+SLD1) and a P+ shielding region at the trench bottom (P+SLD2), which collectively protect the gate trench. To alleviate the JFET effect, two current spreading layers (CSLs) are introduced (DSC-TMOS). Furthermore, through layout design, the P+ shielding regions at the trench bottom are periodically grounded in the direction perpendicular to the trench. Simulation results indicate that the peak electric field in the gate oxide ($E_{\text {ox, peak }}$) is1|.06 $\mathrm{MV} / \mathrm{cm}$ at a drain bias of 1200 V, with a specific onresistance ($R_{\mathrm{on}, \mathrm{sp}}$) of $2.08 \mathrm{~m} \Omega \cdot \mathrm{~cm}^{2}$. To provide guidance for further device optimization, the effects of both the P+SLD2 at the trench bottom and the second current spreading layer (CSL2) on device performance were systematically investigated. The fabricated device was packaged in a TO-247 format. Testing results of the packaged device demonstrate a breakdown voltage (BV) of approximately 1600 V and a $R_{\text {on, sp }}$ of $2.39 \mathrm{~m} \Omega \cdot \mathrm{~cm}^{2}$ under the conditions of $V_{\mathrm{gs}}=20 \mathrm{~V}$ and $I_{\mathrm{d}}=$ 10 A. Furthermore, the device has successfully passed a series of reliability tests, including 1000-hour high-temperature gate bias (HTGB) and highly accelerated temperature and humidity reverse bias (H3TRB) tests.

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