Defect-Aware Built-In Self-Test and Dynamic Repair for Fan-Out Wafer-Level Packaging

Le résumé fourni par la source

Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP faces several manufacturing challenges, such as coefficient of thermal expansion (CTE) mismatch, warpage, die shift, and postmolding protrusion, causing misalignment and bonding issues during redistribution layer (RDL) buildup. In order to address these challenges, we propose a comprehensive defect analysis and testing framework for FOWLP interconnects. We use Ansys Q3D to map defects to equivalent electrical circuit models and perform fault simulations to investigate the impacts of these defects on chiplet functionality. Additionally, we present a built-in self-test (BIST) architecture to detect stuck-at (SA) and bridging faults while accurately diagnosing the fault type and location. We also show how fault signatures can be propagated and decoded across multichiplet interfaces to initiate dynamic repair. To enhance postfabrication yield and reliability, we introduce a priority-based dynamic repair scheme aligned with the universal chiplet interconnect express (UCIe) specification that maximizes repairability without incurring additional hardware overhead in the I/O PHY. This framework offers a practical path toward robust and efficient testability in the next-generation advanced packaging.

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