A 9.4-pA/√Hz Monolithically Integrated Optical Receiver Using Multidrive Noise Cancellation Technique in 45-nm CMOS SOI-Photonic Process

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This article proposes a low-noise monolithically integrated 80-Gbps PAM4 optical receiver using multidrive noise cancellation technique. The proposed receiver integrates a multidrive noise-canceling transimpedance stage (MDNC-TIS), a CML-based differential postamplifier, auxiliary analog loops, and a PD on a single chip. The proposed MDNC-TIS comprises a shunt-feedback transimpedance stage (SF-TIS) followed by a multidrive common-source (MD-CS) stage, which reduces transimpedance amplifier (TIA) noise through noise cancellation mechanism. Additionally, the MDNC-TIS demonstrates a gain enhancement which effectively mitigates the noise impact on postamplifier stages. The optical receiver is implemented in a 45-nm CMOS SOI-photonic process. Measurement results show that the realized TIA achieves 64.5 dB$\Omega $transimpedance gain and 28.5-GHz bandwidth with 9.4-pA/$\surd $Hz input-referred noise current density. The opto-electrical time-domain measurement results indicate that the implemented optical receiver chip achieves sensitivity of −9.64 dBm for 80 Gbps PAM4 signal at 2.4E–4 bit error rate (BER) with 0.9 A/W responsivity of PD.

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