Fang-Jyun Yeh

Optical solution for potential EPE improvement by simultaneous in-die overlay and tilt measurements in DRAM HVM

Chengwei Yang, Chun-Hsien Lin, Renliang Wu, J.I. Lee et autres

Optical in die NZO benefit for DRAM manufacturing

Fang-Jyun Yeh, Shang-Hong Tsai, Hsiao-Lun Chu, K. H. Lee et autres

Today, with the accelerating complexity of nanoelectronics for memory applications, in-die overlay metrology has required much tighter control. A typical in-device overlay control strategy utilizes high-voltage SEM metrology across several key layers, but lot and wafer sampling is limited due to low …

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Enable in-die overlay measurement on DRAM storage node by line scan self-calibration method

Fang-Jyun Yeh, Shang-Hong Tsai, Cheng‐An J. Lin, Chengwei Yang et autres

Semiconductor layer-to-layer overlay in manufacturing significantly impacts product quality and yield performance. Good control of device shifting also influences the spatial scale down for the nanoelectronics of memory applications. Advanced node DRAM semiconductor manufacturing requires a tighter in-die overlay budget. Typically, the …

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Scatterometry and machine learning for in-die overlay solution

Fang-Jyun Yeh, Houssam Chouaib

Advanced technology nodes require tighter lithography overlay specifications with higher throughput and lower cost of ownership. Today, with the accelerating complexity of nanoelectronics for memory applications, an increased emphasis is placed on controlling the on-product overlay (OPO) budget. Consequently, accurate in-die overlay …