Jiayoon Ru

A −248-dB FOM ref CS-Fusion PLL Architecture Combining the Advantages of PFD-CP PLLs and Sampling PLLs in a Single Loop

Junyuan Su, Yuxuan Hu, Zherui Zhang, Lei Wang et autres

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A Hybrid Inner–Outer-Product SRAM Compute-in-Memory GEMM Engine With Precision-Adaptive Systolic Dataflow

Wenjie Ren, Meng Wu, Xuelian Ye, Ruohang Xu et autres

cn (code pays fourni par la source)

A 56.2TOPS/W Hybrid-Inner-Outer-Product SRAM Compute-in-Memory Macro for GEMM with Scalable Precision-Adaptive Systolic Dataflow

Wenjie Ren, X. Ye, Rui Xu, Peiyu Chen et autres

This paper presents an efficient SRAM compute-in-memory (CIM) macro design for general matrix multiplication (GEMM). A hybrid inner-outer product architecture is designed to enable long-time weight reusing and short-time input reusing, reducing 1.57-2.69x overall SRAM access. A data-precision-adaptive dataflow is developed to …

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A 0.16 ppm/°C Voltage Reference with On-Chip Self-Heating and Highly Flexible Auto-Calibration High-Order Compensation

Kaixuan Du, Jiayi Wu, Zhixuan Wang, Jiayoon Ru et autres

This paper introduces a sub-ppm$/{ }^{\circ} \mathrm{C}$voltage reference that supports pseudo two-point calibration at room temperature by incorporating a self-heating control loop, thereby reducing calibration costs. The design also features a highly flexible auto-calibration high-order compensation system that is resilient to model …

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A Compact Cost-Effective NB-IoT System-in-Package With Integrated RF Front-End IPD and TX/RX Gain Self-Calibration

Haopei Deng, Wentao Jiang, Jiayi Ye, Fei He et autres

A compact cost-effective Narrowband Internet-of-Things (NB-IoT) System-in-Package (SiP) in mass production is implemented in 55nm CMOS and Integrated Passive Device (IPD) process. The RF front-end components, i.e., inductors and capacitors, are integrated into an IPD die to reduce the Bill of Material …

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A 28nm Multimode Multiband RF Transceiver with Harmonic-Rejection TX and Spur-Avoidance RX Supporting LTE Cat1bis

Fei Song, Zexue Liu, Danping Li, Jiayi Ye et autres

Ubiquitous cellular IoT applications leverage cellular networks to connect devices, which call for diverse data rates. L TE Cat1 bis with a moderate date rate eases the pain points of IoT adoption, which features eDRX and PSM. It satisfies most IoT scenarios …

S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications

Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing et autres

Digital compute-in-memory (DCIM) has advantages of performing robust and efficient high-precision, e.g. floating-point, multiplication and accumulation operations (MACs), compared to analog CIM solutions. Prior DCIMs [1–4] normally adopt dataflow with broadcast inputs and stationary weights, which can only obtain peak energy efficiency …

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30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing

Ying Liu, Yufei Ma, Ninghui Shang, Tianhao Zhao et autres

Recently, brain-inspired spiking neural networks (SNNs) have demonstrated tremendous improvement in energy efficiency (EE) and low power by exploiting highly sparse spikes and event-driven design [1–2]. (top of Fig. 30.2.1) With the same spike-based information carrier, the combination of an SNN and …

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18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS

Guansheng Li, Adesh Garg, Tim He, Ullas Singh et autres

An ADC/DAC-based coherent optical transceiver [1] is a promising technique to boost the throughput of metro/long-haul links beyond 600Gb/s/λ. It leverages the powerful digital signal processors (DSP) in scaled CMOS processes to enable high-spectral-efficiency modulation formats such as dual-polarization quadrature-amplitude modulation (DP-QAM). …

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A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC

Heyi Li, Kaixuan Du, Yuanxin Bao, Yanchi Dong et autres

This article reports an energy/area-efficient zoom capacitance-to-digital converter (CDC)-based CMOS humidity sensor. It achieves the best-in-class error of ±0.8%RH and better figure of merit (FoMw; 87 fJ/c.step) than the state-of-the-art humidity sensors due to the use of the two techniques described in …

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An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique

Ying Liu, Yufei Ma, Wei He, Zhixuan Wang et autres

This article presents a clock-free spiking neural network (SNN) intelligent inference engine (IIE) for artificial intelligence of things (AIoT) sensor nodes, which often operate in random-sparse-event (RSE) scenarios. The IIE drastically reduces the system’s long-term average (LTA) power consumption, improves energy efficiency, …

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An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications

Yiqi Jing, Zhixuan Wang, Linxiao Shen, Yihan Zhang et autres

This paper proposes an information-aware (IA) adaptive data acquisition (ADA) system for the Internet of Things (IoT) applications. The system can obtain valid information adaptively thanks to 1) signal-dependent full-scale feature tracks the amplitude-domain activity of the event; 2) level-crossing (LC) ADC …

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