J.M. Rochelle

Demystifying Law Librarianship

Teresa Miguel-Stearns, J.M. Rochelle

In this third decade of the 21st century, the legal information profession is engaged in dialogue about the perpetually shrinking pools of qualified candidates for law librarian positions. COVID retirements and the Great Resignation have resulted in a nationwide labor shortage and …

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Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

D.M. Binkley, Benjamin J. Blalock, J.M. Rochelle

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A Custom CMOS Integrated Circuit For PET Tomograph Front-end Applications

D.M. Binkley, Michael J. Paulus, M.E. Casey, R. Nutt et autres

A custom CMOS integrated circuit has been designed, prototyped, and evaluated for PET tomograph front-end applications. The integrated circuit reduces the size. cost, and power consumption of existing PET frontend circuits by Over a factor of two. The integrated circuit, fabricated in …

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Time-domain noise analysis of linear timeinvariant and linear time-variant systems using MATLAB and HSPICE

S.C. Terry, Benjamin J. Blalock, J.M. Rochelle, M.N. Ericson et autres

A custom simulation tool that combines HSPICE and MATLAB to enable time-domain noise analysis is reported. The simulation technique is based on computing the statistics of a random process by ensemble averaging and is applicable to both linear time-invariant (LTI) and linear …

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Time-domain noise analysis of linear time-Invariant and linear time-variant systems using MATLAB and HSPICE

S.C. Terry, Benjamin J. Blalock, J.M. Rochelle, M.N. Ericson et autres

A custom simulation tool that combines HSPICE and MATLAB to enable time-domain noise analysis is reported. The simulation technique is based on computing the statistics of a random process by ensemble averaging and is applicable to both linear time-invariant (LTI) and linear …

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A high resolution, extended temperature sigma delta ADC in 3.3V 0.5μm SOS-CMOS

M.N. Ericson, M. Bobrek, A. Bobrek, C.L. Britton et autres

A /spl Sigma//spl Delta/ modulator designed specifically for extended temperature applications is reported. The design is fabricated in a 3.3-V 0.5 /spl mu/m SOS-CMOS process and incorporates a 2-2 cascade architecture allowing operation as either a 2/sup nd/- or 4/sup th/-order modulator. …

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A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

B.K. Swann, Benjamin J. Blalock, L.G. Clonts, D.M. Binkley et autres

An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range …

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Lutetium oxyorthosilicate block detector readout by avalanche photodiode arrays for high resolution animal PET

Bernd J. Pichler, B.K. Swann, J.M. Rochelle, Ronald Nutt et autres

Avalanche photodiodes (APDs) have proven to be useful as light detectors for high resolution positron emission tomography (PET). Their compactness makes these devices excellent candidates for replacing bulky photomultiplier tubes (PMTs) in PET systems where space limitations are an issue. The readout …

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Comparison of a BSIM3V3 and EKV MOST model for a 0.5 um CMOS process and implications for analog circuit design

S.C. Terry, J.M. Rochelle, D.M. Binkley, Benjamin J. Blalock et autres

A BSIM3V3 and EKV model for a standard 0.5 um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5 um to 33 um. In …

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A custom mixed signal CMOS integrated circuit for high performance PET tomograph front-end applications

B.K. Swann, J.M. Rochelle, D.M. Binkley, B.S. Puckett et autres

A custom mixed-signal CMOS integrated circuit has been developed for high performance PET tomograph front-end applications. The ASIC contains four differential, variable-gain, constant bandwidth, amplifiers to receive buffered PMT voltage pulses. All four amplified PMT signals are summed by adding their outputs …

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Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 /spl mu/m CMOS process and implications for analog circuit design

S.C. Terry, J.M. Rochelle, D.M. Binkley, B.J. Blalock et autres

Design requirements for high-density detector front-ends and other high-performance analog systems routinely force designers to operate devices in moderate inversion. However, CMOS models have traditionally not handled this operating region very well. In this paper, the Berkeley Short-Channel IFGET Model (BSIM3V3) and …

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Flicker noise behavior of MOSFETs fabricated in 0.5 /spl mu/m fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion

M.N. Ericson, C.L. Britton, J.M. Rochelle, Benjamin J. Blalock et autres

This paper presents a summary of the measured noise behavior of CMOS MOSFETs fabricated in the Peregrine 0.5 /spl mu/m fully depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics …

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