Design and implementation of a dynamic power-aware secure processing architecture on FPGA using VERILOG HDL

Résumé fourni par la source

This paper describes a power-aware adaptive security architecture for resource-constrained FPGA edge devices. Always on cryptographic modules waste energy during normal operation, so this design activates a 16-bit PRESENT lightweight block cipher only when the input data looks anomalous. A 4-tap symmetric FIR filter smooths the signal in real time, and a dedicated anomaly detector watches the output. Once filtered data crosses an absolute threshold, a BUFGCE integrated clock-gating cell routes the system clock to the secure module and encryption begins. The design was synthesized and implemented on a Xilinx Spartan-6 FPGA at 50 MHz. It’s compact 62 LUTs and 64 flip-flops and the BUFGCE-based clock gating cuts unnecessary switching activity, which should improve dynamic power efficiency. Together, the results show that this event-driven, clock-gated approach can deliver solid cryptographic protection without breaking the energy budget that embedded hardware demands.

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