An efficient ternary full adder design using carry-free ternary half adder and threshold detectors

Le résumé fourni par la source

Abstract This paper presents a ternary full adder (TFA) built with carbon nanotube field-effect transistors (CNTFETs). The design follows a direct ternary processing approach. Two parallel capacitors first sum the two ternary inputs into a numerical value between 0 and 4. Four threshold detectors, each an inverter with a shifted switching point obtained by selecting a specific CNT chirality, read this sum. Their outputs drive a transistor network that produces a carry-free ternary half adder (CFTHA) circuit’s Sum output of 0, V DD /2, or V DD . A successor circuit turns this Sum output into its next logical level. A 2:1 multiplexer (MUX) circuit then picks either the CFTHA’s Sum or the successor value depending on the Carry input. The Carry output comes from the threshold detector signals, depending the Carry input. Simulated with HSPICE and the Stanford 32-nm CNTFET model at 0.9 V, the proposed TFA achieves a delay of 103.9 ps, power of 1.02 µW, PDP of 0.11 fJ, and EDP of 10.96 fJ·ps using only 38 transistors. It outperforms existing designs with PDP improvements of 1.64× to 6.09× and EDP improvements of 2.20× to 11.59×. Monte Carlo simulations and parameter sweeps confirm the circuit keeps its advantage under PVT variations.

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