Study on the Interfacial Behavior of W CMP on SiGe Film for Disruptive Semiconductor Devices

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For over 40 years, semiconductor design rule has been continuously shrunk, but the industry has reached a point where further miniaturization is challenging. As a result, simply scaling down is no longer sufficient for developing new products, and the focus has shifted towards creating disruptive structures. In the development of disruptive structures, the interconnect process is no longer limited to the BEOL(Back-End-of-Line) but is performed across various layers. Consequently, it is not feasible to use Cu interconnects for all interconnect processes; some must be done using W interconnects. [1] This necessitates the development of W CMP technology capable of stopping on diverse materials. In this study, we investigate the passivation performance when W CMP stops on SiGe films, which act as electrodes in devices, and analyzes various factors that may influence this process. Experiment results showed that not only temperature, commonly considered critical in W CMP, but also byproducts generated during W CMP affect the SiGe removal rate. When W bulk CMP and overpolishing steps were performed separately, the SiGe removal amount was significantly lower compared to when they were performed continuously in a single step. Based on this study, we hypothesized that WOx, a byproduct of W CMP, could accelerate the Fenton reaction, thereby increasing the formation rate of SiGeOx. [2,3] To verify this, we conducted SiGe CMP immediately after extensive W CMP on the pad to expose WOx. The results showed a high removal rate for the initial wafers, which gradually saturated as the W byproducts were removed. Based on these results, we reduced 34% of SiGe loss through separation of W bulk CMP and overpolishing step. Since the SiGe film has a role as an electrode in the device, their thickness and uniformity directly impact the device's electrical characteristics, making SiGe thickness control crucial. To minimize SiGe loss and make better uniformity, it is essential to prevent the increase in SiGe removal rate caused by WOx. The most effective approach is to separate the hardware for W bulk CMP and subsequent overpolishing steps. If this is not feasible due to equipment limits, adding a cleansing step, such as ex-situ conditioning or pad rinsing with DIW, between the two steps could be a possible alternative. Reference K. Ganesh and V. H. Gaidhane, “Tungsten as an interconnect material for Next Generation IC design”, 2020 IEEE International IOT, Electronics and Mechatronics Conference, pp. 1-6 (2020) J. He et al., “Interfacial mechanisms of heterogeneous Fenton reactions catalyzed by iron-based materials: A review” J. Environ. Sci. 97 (2016) Y. Liu and J. Wang, “Multivalent metal catalysts in Fenton/Fenton-like oxidation system: A critical review”, Chemical Engineering Journal 466, 143147 (2023) Figure 1

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