3D‐Topology‐Coordinated Dynamic Load Balancing for Heterogeneous CPU + GPU Accelerated FDTD

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ABSTRACT To fully exploit hardware resources and maximize the computational performance of heterogeneous systems, a 3D‐topology‐coordinated strategy between CPU and GPU is proposed. To address the significant data exchange between hardware devices in existing CPU‐GPU heterogeneous systems—which often results in suboptimal simulation performance—the proposed approach adopts a three‐dimensional domain partitioning scheme for the simulation region. This strategy effectively reduces the volume of inter‐device data transmission. Furthermore, to overcome the workload imbalance caused by varying computational capabilities and hardware affinity across different processors, a dynamic load balancing strategy based on topology‐coordinated strategy is introduced. This method adaptively assigns computational tasks to each device according to real‐time performance metrics, enabling intelligent workload distribution across diverse heterogeneous hardware environments. Simulation results demonstrate that the proposed heterogeneous parallel FDTD method, which integrates dynamic load balancing with spatial partitioning, introduces no additional numerical errors. Compared with traditional serial FDTD implementations on multi‐core CPUs and parallel implementations on multi‐GPU systems, the proposed method achieves speedup factors of up to 872.1× and 2.27×, respectively. This represents a highly attractive enhancement for practical applications.

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