Computational capacity in hydrodynamic real-time hybrid simulation applied to simulate the dynamic response of floating offshore wind turbines

Le résumé fourni par la source

Real-time hybrid simulation (RTHS) mitigates similitude distortions in model-scale testing of floating offshore wind turbines (FOWTs) by coupling physical experiments with numerical models in real time. The real-time coupling requires faster-than-real-time numerical computations to satisfy temporal Froude similitude with the physical experiment, presenting a bottleneck for using higher-fidelity numerical models in RTHS. This paper presents a hydrodynamic-RTHS (hydro-RTHS) framework for FOWTs, which simulates the hydrodynamics physically and the aerodynamics numerically with feedback from the sensor measurements from the physical testing. The framework adapts the three-loop hardware architecture to leverage greater computational resources and mitigate strict temporal requirements, enabling more computationally demanding numerical analyses in hydro-RTHS. The three-loop hardware architecture integrates multiple machines, each dedicated to either the numerical analysis or the RTHS controls, with a rate-transition algorithm to synchronize the tasks executed on the different machines. Virtual and physical tests were used to verify and validate the hydro-RTHS framework, respectively. The virtual tests, which model the physical domain virtually, verified the RTHS implementation to a complete numerical model of the full-scale FOWT prototype simulated in the open-source software, OpenFAST, maintaining comparable control signals while enabling greater computational resources for the numerical calculations. Physical tests demonstrated that the hydro-RTHS framework computes aerodynamic forces similar to the complete OpenFAST model, validating the hydro-RTHS framework using the three-loop hardware architecture. Findings show that the framework is computationally efficient, with reserve capacity to simulate more complex problems due to the customized software, hardware, and the rate-transition algorithm enabled by the three-loop hardware architecture.

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