A Novel Split-Channel LDMOS Using Self-Aligned Technology for Low Q GD and Short-Channel Effect Suppression in High Frequency DrMOS Application

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This paper presents a split-channel LDMOS (SC LDMOS) on a standard 55nm BCD platform to achieve low gate-to-drain charge (QGD) and suppress short-channel effect for high frequency Driver+MOS (DrMOS) application. A NLDD self-aligned implantation technology for SC LDMOS is developed to precisely improve the gate-to-drain overlap length, overcoming short-channel effects such as threshold voltage shifting and leakage increase. Moreover, the simulated surface electric field shows the similar peak to that of conventional LDMOS. In the second channel region, 3.3V constant bias ensures a low RON,SPand optimized BV. Additionally, the QGDof SC LDMOS is optimized without limitation by the design rule of GATE1 length. In the experiments, the SC LDMOS with enhanced channel shows suppression in VTHand leakage shifting. Meanwhile, the BV can be optimized by GATE2 field plate length. A complete low-voltage range of 8~16V class SC LDMOS is demonstrated, which satisfy the basic requirement of RON,SP, covering 2.77 ~ 6.2 mΩ•mm2. The measured on-wafer gate-charge curves confirm an excellent QGDof 0.496 nC/mm2for 12V-class SC LDMOS and illustrate a Miller plateau identical to that of a 16V SC LDMOS due to self-aligned design.

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