A low-power buffer-assisted 14T ternary SRAM

Le résumé fourni par la source

Ternary static random-access memory (TSRAM) has emerged as a promising solution for enhancing energy efficiency and information density beyond binary limits, particularly in data-intensive and low-power applications. This paper presents a power-efficient single-supply 14-transistor CNTFET-based ternary SRAM cell that uses a buffer-based topology with a single-bitline read/write scheme. The proposed design eliminates the need for dual supply rails and redundant voltage-division paths, significantly reducing dynamic power and delay while maintaining robust stability. Extensive HSPICE simulations using the Stanford CNTFET compact model demonstrate superior performance compared to state-of-the-art TSRAM cells, achieving the lowest power-delay product of 5.37 aJ at 0.9 V, along with a competitive static noise margin under process variations. To evaluate practical effectiveness, the proposed TSRAM is integrated into a ternary medical image processing framework using hardware-based signal mapping and a weighted k-nearest neighbor classifier. Application-level results show a 26.65% reduction in average energy consumption, a peak signal-to-noise ratio of 41.06 dB, a mean structural similarity of 99.83%, and a prediction accuracy of 97.86%. A comprehensive figure of merit confirms a 61.58% improvement over existing designs, highlighting the proposed architecture as a strong candidate for energy-efficient ternary biomedical processing systems.

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