A Hardware Architecture for Native Execution of Python Bytecode on FPGA: A Proof-of-Concept

Le résumé fourni par la source

This paper presents a proof-of-concept implementation of a Python virtual machine executed directly on an FPGA using a dedicated, synthesizable microarchitecture described in Verilog. Unlike high-level synthesis (HLS) flows or hardware-oriented domain-specific languages, the proposed approach consumes standard CPython-generated bytecode, preserving Python execution semantics without requiring hardware description language expertise from the developer. The virtual machine follows a stack-based execution model and implements a subset of CPython opcodes, including arithmetic operations, variable storage, and function invocation through built-in calls. A Python-based host tool is used to transmit bytecode instructions to the FPGA and to collect execution results. The proof of concept was implemented and evaluated on a Digilent Basys 3 development board featuring an AMD/Xilinx Artix-7 FPGA. Experimental results demonstrate functional correctness for the supported opcode subset and confirm the feasibility of executing Python bytecode natively in reconfigurable hardware, with performance, resource utilization, and energy consumption metrics establishing a quantitative baseline for the proposed approach.

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