A Benchmark on Directed Graph Representation Learning in Hardware Designs

Le résumé fourni par la source

Fast and accurate evaluation of hardware design quality is essential for agile hardware development. Traditional EDA tools, however, often impose a tradeoff between accuracy and runtime, limiting their effectiveness for modern, highly complex computing systems. In this context, directed graph representation learning (DGRL) has emerged as a powerful paradigm for encoding circuit netlists and computational graphs to enable surrogate modeling of hardware performance. However, DGRL remains relatively underexplored in the hardware domain, mainly due to the absence of comprehensive and user-friendly benchmarks. To address this gap, we present a benchmark that (1) includes six hardware design datasets and 15 prediction tasks spanning multiple levels of circuit abstraction, and (2) provides an extensive evaluation of 21 DGRL models, incorporating diverse graph neural networks (GNNs) and graph transformers (GTs) enhanced with directed-graph-specific positional encodings (PEs). Our results highlight that bidirected (BI) message passing neural networks (MPNNs) and robust PEs significantly enhance model performance. Notably, the top-performing models include PE-enhanced GTs interleaved with BI-MPNN layers and BI-Graph Isomorphism Network, both surpassing baselines across the 15 tasks. Additionally, our investigation into out-of-distribution (OOD) performance emphasizes the urgent need to improve OOD generalization in DGRL models. This benchmark, implemented with a modular codebase, streamlines the evaluation of DGRL models for both hardware and ML practitioners.1.

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