Design of Reliable PUF Cells at Subthreshold

Le résumé fourni par la source

Scalable PUF (Physical Unclonable Function) circuits biased at subthreshold regions with low bit error rates (BER) were designed and characterized. The proposed SRAM-like PUF cells were fabricated using the 90nm CMOS process and occupied an area of$1100 \boldsymbol{F}^{\mathbf{2}}$/bit. By controlling the gate bias voltage of the PUF cells in subthreshold, the measurement results demonstrate good properties of randomness, stability, low bit error rate (BER), and reliability of the PUF cells. Thus, it is a good candidate for high-reliability and low-cost PUF key generation circuits.

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.