Design and Analysis of a Low-Energy Ternary Half-Adder Using GNRFET-Based Unary Operators

Le résumé fourni par la source

Ultra low-power operation is essential for enabling energy harvesting techniques allowing the embedded systems to become self-sustaining and independent of grid power. A key strategy for reducing the critical power consumption in modern embedded design is the adoption of multi-valued logic (MVL). The MVL enables the data compression on physical wires, minimizes interconnections complexity and achieves a lower power consumption over the binary logic. Leveraging the power reducing potential of MVL, this paper introduces a ternary half-adder circuit that achieves reduced power consumption that directly addressing the challenge of maintaining long battery life in embedded and IoT systems. The proposed half adder utilizes dual supply voltage (i.e., 0.5VDDand VDD, respectively) and unary operators to improve delay, power and power delay product (PDP). The presented unary operators and half adder circuits are designed and simulated in HSPICE tool to obtain transient responses. The performances in terms of GNRFET count, delay, power and PDP are analyzed for presented adder circuits and compared to conventional works. The presented half adder showed the performance improvements on average up to 86.99% over existing works.

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