Design of Energy-Efficient Ternary Logic Circuits Utilizing GNR Field-Effect Transistors

Le résumé fourni par la source

Legacy silicon binary circuits are limited by two primary bottlenecks such as high static power leakage and the excessive physical footprint of interconnecting wires. To mitigate these limitations, the multiple-valued logic (MVL) and the adoption of emerging nano-electronic devices represent two promising paradigms for modern circuit design. A novel approach to designing high-performance digital ternary gates with graphene nanoribbon field effect transistors (GNRFETs) is introduced in this study. The GNRFET has unique properties such as modifying the width of graphene nanoribbons (GNRs) to obtain desired threshold voltage values. The novel circuit designs such as Buffer/NOT, NAND/AND and NOR/OR circuits presented in this work. The proposed design logic functions and its complement depends on the control signal (S). Additionally, in these gates, the higher impedance state is presented that helps to save the power while gates are not in use. The presented gates are implemented in HSPICE software to acquire the transient response and performances including delay, power and power delay product (PDP), respectively. Furthermore, the presented gates are compared to the conventional CNTFET based gates in terms of performance. It is noted that the GNRFET gates show an average performance improvement up to 75.40% than the conventional CNTFET gates.

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