Analysis of frequency tuning techniques for SET resilience in ring oscillators using a calibrated SEE model

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Abstract This paper evaluates how frequency tuning techniques, specifically stage count adjustment, gate length scaling, and load capacitance variation affect radiation-induced timing transients in CMOS ring oscillators. A Dynamic Voltage-Dependent (DVD) Single-Event Transient (SET) model, derived from calibrated TCAD simulations of a 65 nm CMOS technology, implemented in Verilog-A, and experimentally validated against heavy-ion data, is employed to simulate realistic n-type and p-type SET current waveforms with voltage-aware drift and diffusion behavior and to assess the impact of frequency tuning strategies on timing degradation in CMOS ring oscillators. To quantify timing sensitivity, both Periodic Steady-State (PSS) impulse-based small-signal and transient simulations are performed under worst-case Process-Voltage-Temperature (PVT) conditions (1.15 V, 75 °C, SS corner). Results show that increasing stage count preserves slew rate and capacitance per node, resulting in negligible variation in SET sensitivity. In contrast, gate length and load capacitance tuning reduce the output slew rate, increasing timing error sensitivity due to degraded current drive and prolonged charge collection. A unified Figure of Merit (FoM) for a given frequency, defined as 1/( P ·Δ t pp ), where P is the total power (in mW) and Δ t pp is the peak-to-peak SET-induced timing error is proposed to evaluate the trade-off between power consumption and SET-induced timing degradation. These findings highlight stage count scaling as the most radiation-tolerant frequency tuning method and demonstrate the utility of the DVD SET model for guiding resilient oscillator design.

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