Design of Quintuple-Node-Upset Hardened Latches Based on C-Element Voting and an Analog Voter

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As nanometer-scale CMOS technology continues to advance, the susceptibility of memory cells to soft errors has significantly increased. Single-event multiple-node upsets (MNUs) have become a critical factor affecting integrated circuit reliability. This paper first proposes a self-recoverable double-node-upset (DNU) hardened latch (DSAR) based on the Soft-Error Aware Read-Decoupled (SAR) latch. Building upon this, a Quad-SAR latch capable of tolerating Quintuple-node upset (QtNU) is designed through dual DSAR redundancy and a two-stage Celement (CE) voting mechanism, achieving an optimized balance in area, power consumption, and delay. Furthermore, to address the high-impedance-state (HIS) sensitivity issue of C-elements, a Quint-SAR latch is achieved in this paper through the implementation of Quintuple-modular redundancy (QMR) combined with an Analog Voter (AV). This structure not only effectively tolerates QtNUs, but its incorporated Analog Voter features HIS insensitivity and offers significant low-overhead advantages compared to traditional voters. Extensive fault injection, PVT fluctuation, and negative bias temperature instability (NBTI) aging effect simulations verify the reliability of the proposed designs. HSPICE simulation results show that both the Quad-SAR and Quint-SAR latches possess QtNU tolerance capability and achieve a good balance in hardware overhead. Quad-SAR is suitable for low-power and low-delay requirements in non-HIS-sensitive scenarios, while Quint-SAR, with its HIS immunity, becomes the preferred solution for high-robustness scenarios. Compared to QNU-hardened and QtNU-hardened latches, their area-power-delay product (APDP) exhibits a decrease of 49.41% and 17.16%, respectively, and their setup time exhibits a decrease of 35.10% and 49.71%, respectively.

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