Gate-Voltage-Conditioned Leakage-Aware Drain Current Prediction in BCAT Using Support Vector Regression

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This paper presents a Support Vector Regression (SVR)-based surrogate modeling framework for fast, gate-voltage-conditioned prediction of leakage-aware drain current in a Buried Channel Array Transistor (BCAT). Accurate current estimation under gate-bias sweeps is essential for modern semi-conductor design because scaling intensifies strong electric-field effects and leakage-related behavior. Using Synopsys Sentaurus TCAD, we generated 1000 bias-point samples over a gate-voltage sweep range under a fixed drain bias, and used the corresponding drain current as the learning target. With systematic preprocessing and hyperparameter optimization, the trained SVR model achieved a test-set accuracy of$R^{2}$= with RMSE=and MAPE=. Cross-validation further showed stable performance (mean$R^{2}$= with standard deviation). The results confirm that SVR can serve as a highly efficient surrogate model, reducing computational cost by several orders of magnitude compared to TCAD while maintaining physically consistent bias-dependent trends.

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