Prediction of Trap Behavior Under Repetitive Short-Circuit Stress in Sic MOSFETs Using Physics-Informed Gaussian Process Regressions

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Silicon carbide (SiC) MOSFETs experience high current and electric-field stress during short-circuit (SC) operation, activating interface traps and causing threshold-voltage shifts. This work examines quasi-steady trap behavior under repetitive SC stress using electro-thermal TCAD with an SRH capture/emission model. A 1.2 kV 4 H -SiC planar MOSFET was simulated with separate channel and JFET regions containing shallow and deep interface traps. Under repeated SC stress-relaxation cycles, channel traps approach quasi-steady occupancy, leading to a saturating threshold-voltage shift, in line with reported experimental trends. We also propose a physics-informed Gaussian process regression (GPR) that maps singlecycle SC descriptors (pulse energy, peak lattice temperature, and first-cycle threshold-voltage shift) to multi-cycle degradation predictions. The model reconstructs multi-cycle trajectories using only a few calibration cycles per condition, reducing the computational cost of brute-force many-cycle simulations.

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