Passing Word Line Row Hammering in DRAM via AI-Assisted Pi-BCAT Structure

Le résumé fourni par la source

We present a device-level analysis of a passing wordline induced disturbance mechanism in scaled DRAM arrays, referred to as Passing Word Line Row Hammering Effect (PWL RHE). The disturbance is driven by repeated switching of passing word lines in dense cell layouts, which introduces strong electrostatic coupling to adjacent storage nodes. Using TCAD-based transient simulations under representative operating biases with floating storage conditions, we observe pronounced node-voltage excursions during PWL transitions. The disturbance is further amplified by charge trapping/de-trapping in isolation-related interface regions, resulting in node deviations that exceed those of conventional row-hammer conditions by orders of magnitude. To reduce the computational burden associated with long transient cycling, a prediction-guided screening flow is incorporated to preselect high-risk coupling cases and avoid redundant simulation sweeps. With this accelerated methodology, an enhanced BCATbased architecture (Pi-BCAT) is shown to significantly suppress PWL-induced node fluctuations compared with a baseline BCAT design, consistent with improved carrier transport control and reduced leakage-sensitive paths. This hybrid framework, combining physics-based TCAD analysis and prediction-assisted exploration, provides a scalable approach for evaluating disturbance-driven degradation and mitigation concepts in next-generation DRAM reliability research.

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