Deep Learning-Based Pareto Optimization Framework for LDMOS Transistors

Le résumé fourni par la source

Laterally Diffused Metal-Oxide Semiconductor (LD-MOS) devices are crucial for high-power and high-frequency applications, but their optimization requires balancing complex trade-offs among structural parameters that determine breakdown voltage (BV), on-resistance ($R_{\text {on }}$), and gate-drain charge$\left(Q_{\text{gd}}\right)$. Conventional single-objective approaches often fail to identify globally optimal solutions across competing performance metrics. This study presents a deep learning-based surrogate modeling framework integrated with multi-objective Pareto optimization for efficient LDMOS design. A ResNet-1D architecture trained on TCAD simulation data accurately predicts electrical characteristics from five key parameters ($L_{1}, N_{1}, T, N_{\text {pwell }}$,$N_{\text {Sub }}$), …, achieving$R^{2}>0.99$while reducing computational cost by up to$53.3 \times$compared with TCAD (Table I). SHAP analysis revealed that$\text{B V}$is most sensitive to drift thickness ($T$) through RESURF effects, while$R_{\text {on }}$and$Q_{\text {gd }}$are primarily controlled by channel doping ($N_{1}$). Pareto optimization between BFOM ($\text{B V}^{2} / R_{\text {on }}$) and SFOM ($Q_{\text {gd }} \times R_{\text {on }}$) quantified the inherent trade-off between conduction efficiency and switching loss, enabling systematic identification of application-specific optimal designs. The proposed framework provides a computationally efficient and physically interpretable platform for LDMOS optimization, facilitating rapid design space exploration and goal-aware device engineering for power semiconductor applications.

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