A 12-bit 1-GS/s Single-Channel Pipelined ADC With Open-Loop Floating Inverter Amplifier and Residue-Dependent Integration Time Compensation

Le résumé fourni par la source

A 12-bit 1-GS/s three-stage pipelined analog-to-digital converter (ADC) employing an analog compensation technique to enhance residue amplifier (RA) gain linearity is presented. The proposed residue-dependent integration time compensation (RITC) technique mitigates the compressing nonlinearity in an RA by scaling the integration time for large RA input signals. This technique leverages the time residue generated by the time-domain (TD) sub-ADC to track the variation of the voltage residue. Corresponding mathematical analyses are incorporated to elaborate on its effectiveness. Benefitting from the RITC technique, the prototype ADC achieves high linearity while consuming 5.1 mW from a 1-V power supply and operating at 1 GS/s. The signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 61.3 and 75.7 dB with a Nyquist input, respectively, leading to a 171.2-dB Schreier figure-of-merit (FoM) and 5.4-fJ/conversion-step Walden FoM.

Ce résumé expose les affirmations des auteurs. BNTIC ne l’interprète pas comme une validation indépendante des résultats.